ACCUMULATION FIELD EFFECT MICROELECTRONIC DEVICE AND PROCESS FOR THE FORMATION THEREOF

• US 20080251862A1
• Filed: 04/14/2008
• Published: 10/16/2008
• Est. Priority Date: 04/12/2007
• Status: Active Grant

• Current Assignee: Penn State Research Foundation
• Original Assignee: Penn State Research Foundation
• Inventors: Fonash, Stephen J., Shan, Yinghui, Ashok, S.
• Granted Patent: US 8,569,834 B2
• Time in Patent Office: Days
• US Class Current: 257/408
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78672 Polycrystalline or microcrystalline silicon transistor
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.

Claims

1. A gated microelectronic device comprising:

a source with a source ohmic contact having a source dopant type and a source dopant concentration and deforming a source linear extent and a source thickness;

a drain with a drain ohmic contact having a drain dopant type and drain dopant concentration and defining a drain linear extent and a drain thickness a channel portion intermediate between said source and said drain, said channel portion having a channel portion dopant type and channel portion dopant concentration and defining a channel portion linear extent and a channel portion thickness;

said channel portion having a dimension normal to the gate suitable to fully deplete in an off-state;

an insulative dielectric in contact with said channel portion;

a gate overlying said insulative dielectric;

a gate contact applying a gate voltage bias to control charge carrier accumulation and depletion in said channel portion;

the source dopant, the drain dopant, and the channel portion dopant are all of a same type

2. The device of claim 1 wherein at least one of said source ohmic contact and said drain ohmic contact is non-contiguous with said channel portion.

3. The device of claim 1 wherein the doping type is p-type and the gate voltage bias is negative and the drain voltage bias is negative to yield a device on-state status.

4. The device of claim 1 wherein the doping type is p-type and the gate voltage bias is positive and the drain voltage bias is negative to yield a device off-state status.

5. The device of claim 1 wherein the source dopant concentration and the drain dopant concentration are equivalent.

6. The device of claim 5 wherein the source dopant concentration is between 10¹² per cm³ and 10¹⁹ per cm³.

7. The device of claim 1 wherein the source dopant concentration is between 1012 per cm³ and 10¹⁹ per cm³.

8. The device of claim 1 wherein the source linear extent and the drain linear extent creates a minority carrier density in said source and said drain proximal to channel edges that is substantially equivalent under the gate voltage bias that is conducive to an inversion layer formation to that found in a thermodynamic equilibrium

9. The device of claim 1 wherein the dimension of said channel region normal to the gate is of between 5 and 100 nanometers.

10. The device of claim 1 wherein said channel portion is an ultra thin semiconductor or a semiconductor ribbon having a thickness of between 5 and 100 nanometers.

11. The device of claim 1 wherein said channel portion is a semiconductor nanowire having a diameter of between 5 and 100 nanometers.

12. The device of claim 1 wherein said channel portion is formed from a semiconductor selected from the group comprising:

organic semiconductors, silicon, germanium, II-VI semiconductors, III-V semiconductors, and carbon materials.

13. The device of claim 1 wherein said channel portion is formed from a material selected from the group consisting of:

silicon on insulator, thin film silicon, a silicon nanowire, a nanoribbon, or nanotube, and carbon nanotube.

14. The device of claim 1 wherein said channel portion is formed from a material selected from the group consisting of:

a grown or deposited thin film semiconductor, semiconductor nanowire, nanoribbon, or nanotube.

15. The device of claim 1 wherein said device is used for controlling currents or voltages in display applications.

16. The device of claim 1 wherein said device is used in electrostatic protection.

17. The device of claim 1 wherein said device is used in sensor applications.

18. The device of claim 1 wherein said device is used in circuit element applications.

19. The device of claim 1 further comprising a second gate intermediate between said source and said drain.

20. A process for producing a gated microelectronic device of claim 1 comprising:

producing said source, drain and channel portions using a nanowire, nanoribbon or nanotube wherein said nanowire, nanoribbon or nanotube is produced by a grow-in-place technique; and

forming successively thereon in said channel region said insulative dielectric and said gate.

21. The process of claim 20 wherein said nanowire, nanoribbon or nanotube is produced by the grow-in-place technique in which a growth channel template is first located on a mother substrate.

22. The process of claim 21 further comprising using said growth channel template on said mother substrate has a sacrificial layer above said mother substrate which serves for release of said template, a floor layer above the sacrificial layer to support a transfer of said template and an optional transfer layer above the template where said transfer layer above template.

23. The process of claim 22 further comprising providing a transfer layer above said growth channel template.

24. The process of claim 23 further comprising moving said transfer layer of said template to a final device substrate.

25. The process of claim 21 wherein said template is transferred from said mother substrate and stamped onto a final device substrate.