CHIP PACKAGE

• US 20080251940A1
• Filed: 04/10/2008
• Published: 10/16/2008
• Est. Priority Date: 04/12/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lo, Hsin-Jung
• Granted Patent: US 7,964,961 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05681 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/11912 : the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49531 : the additional leads being a wiring board
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/50 : Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/86 : using tape automated bonding [TAB]
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A chip package includes a semiconductor chip, a flexible circuit film and a substrate. The substrate has a circuit structure in the substrate. The flexible circuit film is connected to the circuit structure of the substrate through metal joints, an anisotropic conductive film or wireboning wires. The semiconductor chip has fine-pitched metal bumps having a thickness of between 5 and 50 micrometers, and preferably of between 10 and 25 micrometers, and the semiconductor chip is joined with the flexible circuit film by the fine-pitched metal bumps using a chip-on-film (COF) technology or tape-automated-bonding (TAB) technology. A pitch of the neighboring metal bumps is less than 35 micrometers, such as between 10 and 30 micrometers.

Claims

1. A chip package comprising:

a substrate comprising multiple insulating layers and multiple metal circuit layers between said multiple insulating layers;

a flexible circuit film over a top surface of said substrate, wherein said flexible circuit film comprises a first polymer layer over said top surface, a first metal trace on said first polymer layer, a second metal trace on said first polymer layer and a second polymer layer on said first and second metal traces and on said first polymer layer;

a first tin-containing joint between said first metal trace and a first pad of said top surface, wherein said first metal trace is connected to said first pad through said first tin-containing joint;

a second tin-containing joint between said second metal trace and a second pad of said top surface, wherein said second metal trace is connected to said second pad through said second tin-containing joint;

a semiconductor chip directly over said top surface;

a first metal bump between said semiconductor chip and said first metal trace, wherein said semiconductor chip is connected to said first metal trace through said first metal bump; and

a second metal bump between said semiconductor chip and said second metal trace, wherein said semiconductor chip is connected to said second metal trace through said second metal bump, and wherein a pitch between said first and second metal bumps is less than 35 micrometers.

2. The chip package of claim 1 further comprising a third polymer layer on said second polymer layer, on said semiconductor chip, and over said top surface.

3. The chip package of claim 1, wherein a bottom surface of said substrate comprises a third pad connected to said first pad through said multiple metal circuit layers, and a fourth pad connected to said second pad through said multiple metal circuit layers.

4. The chip package of claim 3 further comprising a third tin-containing joint on said third pad, and a fourth tin-containing joint on said fourth pad.

5. The chip package of claim 1, wherein said first polymer layer has a thickness between 10 and 100 micrometers.

6. The chip package of claim 1, wherein said first metal trace comprises a copper layer having a thickness between 3 and 30 micrometers.

7. The chip package of claim 1, wherein said second polymer layer has a thickness between 5 and 30 micrometers.

8. The chip package of claim 1, wherein said first metal bump comprises a gold layer having a thickness between 5 and 50 micrometers.

9. The chip package of claim 1, wherein said first metal bump comprises a copper layer having a thickness between 0.5 and 45 micrometers.

10. The chip package of claim 1, wherein said first metal bump comprises a nickel layer having a thickness between 0.5 and 5 micrometers.

11. The chip package of claim 1, wherein said first metal bump comprises a copper layer having a thickness between 0.5 and 45 micrometers, a nickel layer having a thickness between 0.5 and 5 micrometers on said copper layer, and a gold layer having a thickness between 0.1 and 4.5 micrometers on said nickel layer.

12. The chip package of claim 1, wherein said first metal bump comprises a copper layer having a thickness between 0.5 and 45 micrometers, and a gold layer having a thickness between 0.1 and 4.5 micrometers on said copper layer.

13. The chip package of claim 1, wherein said multiple insulating layers comprise multiple ceramic layers.

14. The chip package of claim 1, wherein said multiple insulating layers comprise multiple organic layers.

15. A chip package comprising:

a substrate comprising multiple insulating layers and multiple metal circuit layers between said multiple insulating layers;

a flexible circuit film over a top surface of said substrate, wherein said flexible circuit film comprises a first polymer layer over said top surface, a first metal trace on said first polymer layer, a second metal trace on said first polymer layer and a second polymer layer on said first and second metal traces;

an anisotropic conductive film (ACF) between said first metal trace and a first pad of said top surface and between said second metal trace and a second pad of said top surface, wherein said first metal trace is connected to said first pad through multiple first metal particles in said anisotropic conductive film, and said second metal trace is connected to said second pad through multiple second metal particles in said anisotropic conductive film;

a semiconductor chip over said flexible circuit film and directly over said top surface;

a first metal bump between said semiconductor chip and said first metal trace; and

a second metal bump between said semiconductor chip and said second metal trace, wherein a pitch between said first and second metal bumps is less than 35 micrometers.

16. The chip package of claim 15, wherein a bottom surface of said substrate comprises a third pad connected to said first pad through said multiple metal circuit layers, and a fourth pad connected to said second pad through said multiple metal circuit layers.

17. The chip package of claim 16 further comprising a third tin-containing joint on said third pad, and a fourth tin-containing joint on said fourth pad.

18. The chip package of claim 15, wherein said first metal bump comprises a gold layer having a thickness between 5 and 50 micrometers.

19. The chip package of claim 15, wherein said first metal bump comprises a copper layer having a thickness between 0.5 and 45 micrometers.

20. The chip package of claim 15, wherein said first metal bump comprises a nickel layer having a thickness between 0.5 and 5 micrometers.