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MEMORY UNIT

  • US 20080253189A1
  • Filed: 04/16/2007
  • Published: 10/16/2008
  • Est. Priority Date: 04/16/2007
  • Status: Active Grant
First Claim
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1. A memory unit, comprising:

  • a first load unit, having a first end coupled to a first voltage, and a second end coupled to a first contact;

    a second load unit, having a first end coupled to the first voltage, and a second end coupled to a second contact;

    a first metal-oxide-semiconductor (MOS) transistor, having a first end coupled to the first contact, a second end coupled to a second voltage, and a gate coupled to the second contact;

    a second MOS transistor, having a first end coupled to the second contact, a second end coupled to a third voltage, and a gate coupled to the first contact;

    a first non-volatile device having a split-gate structure, and having a control gate coupled to a first control bias voltage, a select gate coupled to a first select bias voltage, a first end coupled to the first contact, and a second end coupled to a first bit line; and

    a second non-volatile device having a split-gate structure, and having a control gate coupled to a second control bias voltage, a select gate coupled to a second select bias voltage, a first end coupled to the second contact, and a second end coupled to a second bit line.

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