MEMORY UNIT

• US 20080253189A1
• Filed: 04/16/2007
• Published: 10/16/2008
• Est. Priority Date: 04/16/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Kuo, Ming-Chang
• Granted Patent: US 7,512,000 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The memory unit not only has the advantage of high speed operation of a static random access memory, but also functions as a non-volatile memory for saving data.

Claims

1. A memory unit, comprising:

a first load unit, having a first end coupled to a first voltage, and a second end coupled to a first contact;

a second load unit, having a first end coupled to the first voltage, and a second end coupled to a second contact;

a first metal-oxide-semiconductor (MOS) transistor, having a first end coupled to the first contact, a second end coupled to a second voltage, and a gate coupled to the second contact;

a second MOS transistor, having a first end coupled to the second contact, a second end coupled to a third voltage, and a gate coupled to the first contact;

a first non-volatile device having a split-gate structure, and having a control gate coupled to a first control bias voltage, a select gate coupled to a first select bias voltage, a first end coupled to the first contact, and a second end coupled to a first bit line; and

a second non-volatile device having a split-gate structure, and having a control gate coupled to a second control bias voltage, a select gate coupled to a second select bias voltage, a first end coupled to the second contact, and a second end coupled to a second bit line.

2. The memory unit according to claim 1, wherein the first non-volatile device and the second non-volatile device respectively comprises:

a substrate, having a source region and a drain region;

a charge-trapping layer, disposed on part of the area of the substrate;

a control gate, disposed on the charge-trapping layer;

a select gate, covering part of the area of the substrate and part of the area of the control gate; and

at least one gate dielectric layer, disposed between the select gate and the substrate, between the select gate and the charge-trapping layer and between the select gate and the control gate.

3. The memory unit according to claim 2, wherein the charge-trapping layer sequentially comprises an oxide layer, a nitride layer and an oxide layer.

4. The memory unit according to claim 3, wherein a material of the oxide layer comprises silicon oxide.

5. The memory unit according to claim 3, wherein a material of the nitride layer comprises silicon nitride.

6. The memory unit according to claim 3, wherein a material of the gate dielectric layer comprises silicon oxide.

7. The memory unit according to claim 1, wherein the first non-volatile device and the second non-volatile device respectively comprises:

a substrate, having a source region and a drain region;

a floating gate, disposed on part of the area of the substrate;

a control gate, disposed on part of the area of the floating gate;

a select gate, covering part of the area of the substrate and part of the area of the floating gate; and

at least one gate dielectric layer, disposed between the select gate and the substrate, between the select gate and the floating gate, between the substrate and the floating gate and between the floating gate and the control gate.

8. The memory unit according to claim 7, wherein a material of the gate dielectric layer comprises silicon oxide.

9. The memory unit according to claim 1, wherein the first load unit and the second load unit are depletion transistors, P-type metal-oxide-semiconductor transistors, thin film transistors or resistors.

10. The memory unit according to claim 1, wherein the first MOS transistor and the second MOS transistor are N-type metal-oxide-semiconductor transistors.