Non-Volatile Memory with Predictive Programming

• US 20080253193A1
• Filed: 04/10/2007
• Published: 10/16/2008
• Est. Priority Date: 04/10/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian
• Granted Patent: US 7,551,483 B2
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. A checkpoint is a set of coordinates on the predetermined function determined by a conventional programming mode employing alternating program and verify operations.

Claims

1. A nonvolatile memory, comprising:

an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels;

read/write circuits for reading and programming a page of memory cells in parallel;

a state machine for controlling the operation of said non-volatile memory including said read/write circuits, said state machine;

providing a predetermined function for a memory cell under programming, the function yielding programming voltage value as a function of threshold voltage level a memory cell is targeted to be programmed thereto;

controlling programming the memory cell to the target threshold voltage level with a programming voltage having increasing amplitude; and

stopping programming of the memory cell after the programming voltage has substantially reached a value as determined by the predetermined function evaluated at the target threshold voltage level.

2. The nonvolatile memory as in claim 1, wherein the programming voltage having increasing amplitude is a series of voltage pulses.

3. The nonvolatile memory as in claim 1, wherein the predetermined function is substantially a linear function.

4. The nonvolatile memory as in claim 1, wherein said state machine providing a predetermined function further includes:

designating a checkpoint of the function as a designated checkpoint threshold voltage level programmable by a corresponding checkpoint programming voltage value;

determining the corresponding checkpoint programming voltage value by alternately programming and verifying until the checkpoint threshold voltage level is program-verified; and

calibrating the predetermined function to yield the checkpoint programming voltage value when evaluated at the checkpoint threshold voltage level before being used to determine a programming voltage value for programming the memory cell to the target threshold voltage level.

5. The nonvolatile memory as in claim 4, wherein the target threshold voltage level is less than a predetermined voltage from the checkpoint threshold voltage level.

6. The nonvolatile memory as in claim 4, wherein one or more checkpoint threshold voltage level is designated among the range of threshold voltage levels.

7. The nonvolatile memory as in claim 4, wherein the predetermined function is linear and is defined by an estimated slope and a checkpoint.

8. The nonvolatile memory as in claims 4, wherein the predetermined function is substantially linear and is defined by at least two checkpoints.

9. The nonvolatile memory as in claim 1, wherein the nonvolatile memory has memory cells that individually store more than one bit of data.

10. The nonvolatile memory as in claim 1, wherein the nonvolatile memory has memory cells that individually store data as an amount of charge programmed into a charge storing element.

11. The nonvolatile memory as in claim 1, wherein the charge storing element is a floating gate of a field effect transistor.

12. The nonvolatile memory as in claim 1, wherein the charge storing element is a dielectric layer in a field effect transistor.

13. The nonvolatile memory as in claim 1, wherein the nonvolatile memory has memory cells with a NAND structure.

14. The nonvolatile memory as in claim 1, wherein the non-volatile memory is a flash EEPROM.

15. The nonvolatile memory as in claim 1, wherein the nonvolatile memory is embodied in a memory card.

16. The nonvolatile memory as in claim 1, wherein the nonvolatile memory is embedded in a computing device.

19. A nonvolatile memory as in any one of claims 1-18, wherein the memory cell is one of a group of memory cells being programming together.

17. A nonvolatile memory, comprising:

an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels;

means for providing a predetermined function for a memory cell under programming, the function yielding programming voltage value as a function of threshold voltage level a memory cell is targeted to be programmed thereto;

means for controlling programming the memory cell to the target threshold voltage level with a programming voltage having increasing amplitude; and

means for stopping programming of the memory cell after the programming voltage has substantially reached a value as determined by the predetermined function evaluated at the target threshold voltage level.

18. The nonvolatile memory as in claim 17, further comprising:

means for designating a checkpoint of the function as a designated checkpoint threshold voltage level programmable by a corresponding checkpoint programming voltage value;

means for determining the corresponding checkpoint programming voltage value by alternately programming and verifying until the checkpoint threshold voltage level is program-verified; and

means for calibrating the predetermined function to yield the checkpoint programming voltage value when evaluated at the checkpoint threshold voltage level before being used to determine a programming voltage value for programming the memory cell to the target threshold voltage level.