MULTICAST AND BROADCAST OPERATIONS IN ETHERNET SWITCHES

• US 20080253371A1
• Filed: 06/23/2008
• Published: 10/16/2008
• Est. Priority Date: 12/03/2001
• Status: Abandoned Application

• Current Assignee: Rahul Saxena
• Original Assignee: Rahul Saxena
• Inventors: Saxena, Rahul
• Application Number:
  US12/143,994
• Publication Number:
  US 20080253371A1
• Time in Patent Office: Days
• US Class Current: 370/390
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/252 Store and forward routing
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

A switch and a process of operating a switch are described where a received data frame is copied one or more times into a memory before being transmitted out of the switch. The switch and method determine how much space in the memory is needed to store all of the copies of the received data frame and then the switch and method determine locations in the memory for storing the copies of the received data frames. The copies of the received data frame are stored until the ports designated as transmitting the copies of the received data frame are ready. When a port is ready, a copy of the received data frame is read out of the memory and the port is instructed where to locate the copy on a bus. When the port has retrieved the copy of the data frame, it transmits the data frame out of the switch.

Claims

1. A switching apparatus comprising:

a first port coupled to receive an input data frame;

a first logic circuit coupled to receive the input data frame from the first port and configured to determine a number of copies of the input data frame to make and to make the number of copies of the input data frame;

a first memory coupled to the first logic circuit and configured to store and read the copies of the input data frame;

a second logic circuit coupled to the first memory and configured to determine when to read at least one copy of the input data frame from the first memory; and

a second port coupled to the first memory and configured to transmit the at least one copy of the input data frame.

2. The switching apparatus of claim 1 wherein the first logic circuit further comprises a third logic circuit configured to determine one or more empty locations in the first memory to store the copies of the input data frame.

3. The switching apparatus of claim 2 wherein the first logic circuit further comprises a second memory configured to keep track of all of the empty locations in the first memory.

4. The switching apparatus of claim 3 wherein:

the first memory is comprised of channels and segments, and the third logic circuit is configured to determine where there are empty channels in the first memory to store the copies of the input data frame.

5. The switching apparatus of claim 3 wherein:

the first memory is comprised of channels and segments, and the third logic circuit is configured to determine where there is at least one empty segment in the first memory to store one of the copies of the input data frame.

6. The switching apparatus of claim 2 wherein the first memory is comprised of channels that each includes segments such that each segment in each channel is independently addressable.

7. The switching apparatus of claim 1 wherein the first logic circuit further comprises a third logic circuit configured to determine how many additional ports will output some of the copies of the input data frame and to calculate the minimum amount of storage space that is necessary to store all of the necessary copies of the input data frame in the first memory.

8. The switching apparatus of claim 6 wherein the first logic circuit further comprises a fourth logic circuit configured to determine the size of the input data frame such that the size of the input data frame is used to calculate the minimum amount of storage space necessary to store the copies of the input data frame.

9. The switching apparatus of claim 8 wherein the first memory is addressable by channels and segments and the first logic circuit is configured to determine how many channel and segment addressable locations are needed to store the number of copies of the input data frame.

10. The switching apparatus of claim 1 wherein the first memory is distributed across the switch.

11. The switching apparatus of claim 1 further comprising a bus coupled with the first memory and the second port and configured to transmit data including at least one copy of the input data frame from the first memory to the second port.

12. The switching apparatus of claim 11 wherein the second port comprises a third logic circuit configured to select the at least one copy of the input data frame from the bus.

13. The switching apparatus of claim 1 wherein the second logic circuit is further configured to indicate a location in the first memory where the second port is to obtain the at least one data frame for transmitting.

14. A switching apparatus comprising:

a first logic circuit coupled to receive an input data frame and configured to determine a number of copies of the input data frame to make and to make the determined number of copies of the input data frame;

a memory coupled to the first logic circuit and configured to store and read the copies of the input data frame, the memory being comprised of channels and segments with one or more segments being accessible at a given time; and

a second logic circuit coupled to the memory and configured to determine when to read at least one copy of the input data frame from the memory.

15. The switching apparatus of claim 14 further comprising a third logic circuit configured to determine one or more empty locations in the memory to store the copies of the input data frame.

16. The switching apparatus of claim 15 wherein the memory is comprised of channels and segments and the third logic circuit is configured to determine where there are empty channels in the memory for storing copies of the input data frame.

17. The switching apparatus of claim 15 wherein the third logic circuit is configured to determine where there is at least one empty segment in the memory for storing at least one copy of the input data frame.

18. The switching apparatus of claim 14 further comprising a plurality of ports and wherein the first logic circuit comprises a third logic circuit configured to determine how many of the plurality of ports will output some of the number of copies of the input data frame and to calculate the minimum amount of storage space necessary to store all of the necessary copies of the input data frame in the memory.

19. The switching apparatus of claim 14 wherein the first logic circuit further comprises a fourth logic circuit configured to determine the size of the input data frame in calculating the minimum amount of storage space to store the necessary copies of the input data frame in the memory.

20. The switching apparatus of claim 19 wherein the first logic circuit is configured to determine how many channel addressable locations and segment addressable locations are needed to store the copies of the input data frame.