Method for forming a semiconductor structure having nanometer line-width
First Claim
1. A method for forming a semiconductor structure having a deep sub-micron or nano scale feature size, comprising:
- providing a semiconductor substrate;
forming a first photoresist layer on said semiconductor substrate;
forming a second photoresist layer on said first photoresist layer;
carrying out an exposure procedure on said first and said second photoresist layer with a proper exposure energy;
developing said second photoresist layer while not developing said first photoresist layer to form a first resist groove on said substrate; and
carrying out an anisotropic etching process on said first resist groove with a proper angle to a normal line for a surface of said substrate to form a second resist groove.
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Abstract
A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the Γ-shaped metal gate with nano scale line-width can be formed.
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Citations
14 Claims
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1. A method for forming a semiconductor structure having a deep sub-micron or nano scale feature size, comprising:
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providing a semiconductor substrate; forming a first photoresist layer on said semiconductor substrate; forming a second photoresist layer on said first photoresist layer; carrying out an exposure procedure on said first and said second photoresist layer with a proper exposure energy; developing said second photoresist layer while not developing said first photoresist layer to form a first resist groove on said substrate; and carrying out an anisotropic etching process on said first resist groove with a proper angle to a normal line for a surface of said substrate to form a second resist groove. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for forming a semiconductor structure having a deep sub-micron or nano scale feature size, comprising:
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providing a semiconductor substrate; forming a first photoresist layer on said semiconductor substrate; forming a second photoresist layer on said first photoresist layer; forming a third photoresist layer on said second photoresist layer; carrying out an exposure procedure on said first, second and third photoresist layers with a proper exposure energy; developing said second and said third photoresist layers while not developing said first photoresist layer to form a first resist groove on said substrate; and carrying out an anisotropic etching process on said first resist groove with a proper angle to a normal line for a surface of said substrate to form a second resist groove. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification