Method for forming a semiconductor structure having nanometer line-width

• US 20080254632A1
• Filed: 04/10/2007
• Published: 10/16/2008
• Est. Priority Date: 04/10/2007
• Status: Active Grant

• Current Assignee: National Chiao Tung University (Government of The Republic of China)
• Original Assignee: National Chiao Tung University (Government of The Republic of China)
• Inventors: Chang, Edward Yi, Chen, Szu-Hung, Lien, Yi-Chung
• Granted Patent: US 7,501,348 B2
• Time in Patent Office: Days
• US Class Current: 438/701
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 29/42312 Gate electrodes for field effect devices

Abstract

A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the Γ-shaped metal gate with nano scale line-width can be formed.

Claims

1. A method for forming a semiconductor structure having a deep sub-micron or nano scale feature size, comprising:

providing a semiconductor substrate;

forming a first photoresist layer on said semiconductor substrate;

forming a second photoresist layer on said first photoresist layer;

carrying out an exposure procedure on said first and said second photoresist layer with a proper exposure energy;

developing said second photoresist layer while not developing said first photoresist layer to form a first resist groove on said substrate; and

carrying out an anisotropic etching process on said first resist groove with a proper angle to a normal line for a surface of said substrate to form a second resist groove.

2. The method according to claim 1, wherein said first resist groove is under-cut structure.

3. The method according to claim 1, wherein said anisotropic etching comprises dry etching.

4. The method according to claim 1, wherein said proper angle comprises an included angle.

5. The method according to claim 1, further comprising:

depositing metal layer on said substrate with said second resist groove; and

removing said first photoresist layer, said second photoresist layer and part of said metal layer to form a metal electrode.

6. The method according to claim 5, wherein said metal layer comprises multiple metal elements.

7. The method according to claim 5, wherein said removing process comprises a lift-off process.

8. A method for forming a semiconductor structure having a deep sub-micron or nano scale feature size, comprising:

providing a semiconductor substrate;

forming a first photoresist layer on said semiconductor substrate;

forming a second photoresist layer on said first photoresist layer;

forming a third photoresist layer on said second photoresist layer;

carrying out an exposure procedure on said first, second and third photoresist layers with a proper exposure energy;

developing said second and said third photoresist layers while not developing said first photoresist layer to form a first resist groove on said substrate; and

carrying out an anisotropic etching process on said first resist groove with a proper angle to a normal line for a surface of said substrate to form a second resist groove.

9. The method according to claim 8, wherein said first resist groove is under-cut structure.

10. The method according to claim 8, wherein said anisotropic etching comprises dry etching.

11. The method according to claim 8, wherein said proper angle comprises an included angle.

12. The method according to claim 8, further comprising:

depositing metal layer on said substrate with said second resist groove; and

removing said first photoresist layer, said second photoresist layer, said third photoresist layer and part of said metal layer to form a metal electrode.

13. The method according to claim 12, wherein said metal layer comprises multiple metal elements.

14. The method according to claim 12, wherein said removing process comprises a lift-off process.