SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD FOR THE SAME
First Claim
1. A semiconductor integrated circuit comprising a clock distribution circuit for distributing a clock signal in a functional block constructed by using standard cells, the clock distribution circuit including:
- a first clock main line extending along a first direction;
a first clock branch line group including a plurality of clock branch lines extending along a second direction perpendicular to the first direction and electrically connected to the first clock main line;
a first clock driving cell electrically connected to the first clock main line;
a first clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the first clock main line or the first clock branch line group;
a second clock main line extending in parallel to the first clock main line;
a second clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the second clock main line;
a second clock driving cell electrically connected to the second clock main line;
a second clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the second clock main line or the second clock branch line group; and
a clock source driver for providing a clock signal to the first clock driving cell and the second clock driving cell,the first clock branch line group being electrically separated from the second clock branch line group,the first clock driving cell singly driving the first clock main line and the first clock branch line group,the second clock driving cell singly driving the second clock main line and the second clock branch line group.
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Accused Products
Abstract
A functional block is divided into a plurality of regions. In each region, a clock main line extending along a first direction, a clock branch line group including a plurality of clock branch lines extending along a second direction perpendicular to the first direction and electrically connected to the clock main line, a clock driving cell electrically connected to the clock main line and a clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the clock main line or the clock branch line group are provided. The clock branch line groups of the respective regions are electrically separated from each other, and the clock driving cell singly drives the clock main line connected thereto and the clock branch line group connected to the clock main line.
34 Citations
19 Claims
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1. A semiconductor integrated circuit comprising a clock distribution circuit for distributing a clock signal in a functional block constructed by using standard cells, the clock distribution circuit including:
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a first clock main line extending along a first direction; a first clock branch line group including a plurality of clock branch lines extending along a second direction perpendicular to the first direction and electrically connected to the first clock main line; a first clock driving cell electrically connected to the first clock main line; a first clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the first clock main line or the first clock branch line group; a second clock main line extending in parallel to the first clock main line; a second clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the second clock main line; a second clock driving cell electrically connected to the second clock main line; a second clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the second clock main line or the second clock branch line group; and a clock source driver for providing a clock signal to the first clock driving cell and the second clock driving cell, the first clock branch line group being electrically separated from the second clock branch line group, the first clock driving cell singly driving the first clock main line and the first clock branch line group, the second clock driving cell singly driving the second clock main line and the second clock branch line group. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A layout method for a semiconductor integrated circuit including a clock distribution circuit for distributing a clock signal, comprising:
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a region dividing step of dividing a functional block including the clock distribution circuit into a plurality of regions along a first direction; a main line placement step of providing a clock main line at a center of each region to extend along the first direction by using an interconnection of an upper layer with a large thickness; a branch line placement step of providing a plurality of clock branch lines to extend along a second direction perpendicular to the first direction with the clock main line set as a center; a driving cell placement/connection step of providing a clock driving cell for driving the clock main line and the clock branch lines at the center of each region and forming a line for connecting the clock driving cell to the clock main line; a clock connection step of forming a line for connecting each clock synchronous cell placed in each region to one of the clock main line and the clock branch lines placed nearby in the same region; and a buffer tree building step of building a buffer tree extending from a clock source driver to the clock driving cell.
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Specification