METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME
First Claim
1. A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more defined failure mechanisms, the method comprising:
- breaking down the integrated circuit device into microarchitecture structures;
further breaking down each structure into one or more of elements and devices, with a device comprising a sub-component of an element;
determining, for each vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into one of a fatal failure and a non-fatal failure, wherein a fatal failure of a given device is one in which the failure causes the element employing the given device to fail;
determining, for those devices whose failures are classified as fatal, one or more of an effective stress degree and an effective stress time based on one or more architecture-level events and states;
determining one or more of a failure rate and a probability of fatal failure for the devices, using the one or more of the associated effective stress degree and effective stress time; and
aggregating the one or more of the failure rate of the devices and the probability of fatal failures of the devices, across the structures for the one or more defined failure mechanisms.
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Accused Products
Abstract
A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.
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Citations
25 Claims
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1. A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more defined failure mechanisms, the method comprising:
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breaking down the integrated circuit device into microarchitecture structures; further breaking down each structure into one or more of elements and devices, with a device comprising a sub-component of an element; determining, for each vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into one of a fatal failure and a non-fatal failure, wherein a fatal failure of a given device is one in which the failure causes the element employing the given device to fail; determining, for those devices whose failures are classified as fatal, one or more of an effective stress degree and an effective stress time based on one or more architecture-level events and states; determining one or more of a failure rate and a probability of fatal failure for the devices, using the one or more of the associated effective stress degree and effective stress time; and aggregating the one or more of the failure rate of the devices and the probability of fatal failures of the devices, across the structures for the one or more defined failure mechanisms. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. (canceled)
Specification