SDRAM convolutional interleaver with two paths

• US 20080256417A1
• Filed: 04/13/2007
• Published: 10/16/2008
• Est. Priority Date: 04/13/2007
• Status: Active Grant

• Current Assignee: Imagine Communications Limited (Gores Broadcast Holdings LLC)
• Original Assignee: RGB Networks, Inc. (Gores Broadcast Holdings LLC)
• Inventors: Andersson, Jorgen
• Granted Patent: US 8,127,199 B2
• Time in Patent Office: Days
• US Class Current: 714/762
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/2732 Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver

Abstract

An SDRAM convolutional interleaver with two paths. Symbols are assigned to a given one of the two paths, then are sorted to minimize (to one) a number of breaks in a sequential Interleaver write address. After sorting, the symbols are stored staggered in SRAM and burst written to SDRAM. Before writing to SDRAM, data is accumulated for four symbols at a time, and the data is written four symbols wide to optimize SDRAM access time. 8 bit symbols are written 32 bits at a time to SDRAM.

Claims

1. A method of interleaving data comprising:

providing two interleaver paths;

receiving a plurality of symbols;

assigning each of the symbols to a given one of the two paths; and

sorting the symbols to minimize a number of breaks in a sequential Interleaver write address.

2. The method of claim 1, wherein:

after sequentially sorting, burst writing the symbols to SDRAM.

3. The method of claim 2, wherein:

after sequentially sorting, there is only one break in the sequential Interleaver write address.

4. The method of claim 1, wherein:

after sequentially sorting, there is only one break in the sequential Interleaver write address.

5. The method of claim 1, further comprising:

providing a plurality of symbol channels.

6. A method of interleaving data comprising:

before writing to SDRAM, performing packing by accumulating data for four FEC symbols at a time; and

writing four symbols wide to optimize SDRAM access time.

7. The method of claim 6, wherein:

the FEC symbols are 8 bits;

data is written 32 bits at a time to SDRAM to fit the SDRAM interface.

8. The method of claim 6, wherein:

two interleaver paths are provided; and

prior to packing, the symbols are sorted to minimize a number of breaks in a sequential interleaver write address.

9. A method of interleaving data comprising:

storing dual path Interleaver data in SDRAM by first writing the data in a staggered pattern in SRAM such that a linear read can be done.

10. The method of claim 9, further comprising:

restarting the staggering within a commutator loop to keep the SRAM small while maintaining the interleaver structure and the burst write feature to the SDRAM.

11. The method of claim 9, wherein:

the data is stored in the SDRAM such that a linear 32 bit read will provide the data stream that represents the stream from the dual path Interleaver.

12. A method of interleaving data which is a sequence of symbols, wherein “

I”

represents an interleaving depth and “

J”

represents an interleaving increment, comprising writing the sequence of symbols to SRAM, the SRAM having a number “

r”

of rows and a number “

c”

columns, by;

(a) writing a first symbol to address located at a first column and a first row of the SRAM;

(b) writing a next-in-the-sequence symbol in a new column which is J columns removed from the previous column, and in a new row of the SRAM which is one row removed from the previous row; and

(c) repeating the step (b) until all the symbols are written to SRAM.

13. The method of claim 12, further providing:

(d) after writing all of the symbols to SRAM, burst writing the data to SDRAM.

14. The method of claim 12, wherein the data is written in a staggered pattern defined by the relationships:

c_new=(c_previous+J) modulo 4, where “

c”

is the column number; and

r_new=(r_previous+1) modulo I, where “

r”

is the row number.

18. The method of claim 14, further comprising:

when the SRAM has a full block corresponding to a SDRAM Burst block, performing a full length burst write from SRAM to SDRAM.

15. A method of interleaving data comprising:

providing two interleaver paths;

providing a plurality of symbol channels;

receiving a plurality of symbols;

assigning each of the symbols to a given one of the two paths;

sorting the symbols to minimize a number of breaks in a sequential Interleaver write address; and

after sequentially sorting, burst writing the symbols to SDRAM;

wherein, after sequentially sorting, there is only one break in the sequential Interleaver write address;

further comprising;

before writing to SDRAM, accumulating data for four FEC symbols at a time; and

writing four symbols wide to optimize SDRAM access time;

wherein;

the FEC symbols are 8 bits;

data is written 32 bits at a time to SDRAM to fit the SDRAM interface, and

data is written to SDRAM in a staggered pattern from SRAM such that a linear read can be done to gain speed.

16. The method of claim 15, further comprising:

restarting the staggering within a commutator loop to keep the SRAM small while maintaining the interleaver structure and the burst write feature to the SDRAM.

17. A method of interleaving data comprising:

receiving a plurality of symbols, wherein each of the symbols is assigned to one of two paths; and

sorting the symbols so that all of the symbols assigned to one of the two paths are grouped together, and all of the symbols assigned to another of the two paths are grouped together; and

using SRAM, packing the sorted symbols in a staggered pattern so that data can be burst written to SDRAM.

19. Apparatus for interleaving data comprising:

means for sorting symbols which are assigned to one of two paths, and grouping the symbols so that a first portion of symbols which are assigned to a given one of the two paths are grouped together and a remaining portion of symbols which are assigned to another given one of the two paths are grouped together;

means for storing the sorted symbols in a staggered pattern so that data can be burst written to SDRAM; and

means for burst writing the symbols to SDRAM.

20. The apparatus of claim 19, wherein:

the means for storing the sorted symbols in a staggered pattern comprises SRAM.