MASK PATTERN DESIGN METHOD AND SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DESIGN PROGRAM

• US 20080256504A1
• Filed: 04/09/2008
• Published: 10/16/2008
• Est. Priority Date: 04/12/2007
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Oishi, Hidetoshi, Oka, Mikio
• Granted Patent: US 8,924,897 B2
• Time in Patent Office: Days
• US Class Current: 716/19
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Abstract

A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.

Claims

1. A mask pattern design method comprising the steps of:

dividing design layout data for a pattern into a plurality of regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of said pattern from the plurality of regions exceeds a predetermined allowance range;

setting a process window of which a plurality of transfer conditions of the pattern data from the region extracted by said process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and

extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with said process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.

2. The mask pattern design method according to claim 1, wherein, in the case that a plurality of regions wherein said transfer dimensions exceed the predetermined allowance range are extracted, a transfer simulation is performed with the various transfer conditions by each of said process windows regarding the various regions, transfer conditions wherein said transfer dimensions for each region exceed the allowance range are extracted, and the occurrence probability for the transfer conditions are summed for each region, following which yield is computed.

3. The mask pattern design method according to claim 1, wherein, with the process to extract any region wherein transfer dimensions obtained from a transfer simulation of said pattern from the plurality of regions exceeds a predetermined allowance range, the transfer dimensions with the transfer simulation performed with the worst conditions of the variability allowance range of a manufacturing process assumed with the pattern transfer device is compared to said predetermined allowance range.

4. The mask pattern design method according to claim 1, wherein, in the case that a plurality of regions wherein said transfer dimensions exceed the predetermined allowance range, the region with a constant having the greatest difference from said predetermined allowance range of the plurality of extracted regions is removed and the remainder are subjected to latter processing.

5. A semiconductor manufacturing method comprising the steps of:

dividing design layout data for a pattern into a plurality of regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of said pattern from the plurality of regions exceeds a predetermined allowance range;

setting a processing window wherein each of a plurality of transfer conditions regarding pattern data of said extracted regions are applied, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window;

extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with said process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition; and

in the case that said computed yield is within a predetermined range, performing pattern transfer with said design layout data, whereby a semiconductor device is manufactured.

6. A semiconductor design program to be executed with a computer, comprising the steps of:

dividing design layout data for a pattern into a plurality of regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of said pattern from the plurality of regions exceeds a predetermined allowance range;

setting a processing window wherein each of a plurality of transfer conditions regarding pattern data of said extracted regions are applied, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and

extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with said process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.