MASK PATTERN DESIGN METHOD AND SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DESIGN PROGRAM
First Claim
1. A mask pattern design method comprising the steps of:
- dividing design layout data for a pattern into a plurality of regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of said pattern from the plurality of regions exceeds a predetermined allowance range;
setting a process window of which a plurality of transfer conditions of the pattern data from the region extracted by said process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and
extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with said process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.
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Abstract
A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.
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Citations
6 Claims
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1. A mask pattern design method comprising the steps of:
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dividing design layout data for a pattern into a plurality of regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of said pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which a plurality of transfer conditions of the pattern data from the region extracted by said process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with said process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition. - View Dependent Claims (2, 3, 4)
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5. A semiconductor manufacturing method comprising the steps of:
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dividing design layout data for a pattern into a plurality of regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of said pattern from the plurality of regions exceeds a predetermined allowance range; setting a processing window wherein each of a plurality of transfer conditions regarding pattern data of said extracted regions are applied, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with said process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition; and in the case that said computed yield is within a predetermined range, performing pattern transfer with said design layout data, whereby a semiconductor device is manufactured.
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6. A semiconductor design program to be executed with a computer, comprising the steps of:
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dividing design layout data for a pattern into a plurality of regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of said pattern from the plurality of regions exceeds a predetermined allowance range; setting a processing window wherein each of a plurality of transfer conditions regarding pattern data of said extracted regions are applied, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with said process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.
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Specification