METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH MASKLESS SUPERLATTICE DEPOSITION FOLLOWING STI FORMATION AND RELATED STRUCTURES

• US 20080258134A1
• Filed: 04/14/2008
• Published: 10/23/2008
• Est. Priority Date: 04/23/2007
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Mears, Robert J., Rao, Kalipatnam Vivek
• Granted Patent: US 7,812,339 B2
• Time in Patent Office: Days
• US Class Current: 257/15
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/15 Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices such structures applied for the control of light G02F1/017, applied in semiconductor lasers H01S5/34

Abstract

A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer. The semiconductor device may further include a lateral spacer between the superlattice layer and the STI region and which may include a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a surface;

a shallow trench isolation (STI) region in said semiconductor substrate and extending above the surface thereof;

a superlattice layer adjacent the surface of said semiconductor substrate and comprising a plurality of stacked groups of layers;

each group of layers of said superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer; and

a lateral spacer between said superlattice layer and said STI region and comprising a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion.

2. The semiconductor device of claim 1 wherein said upper dielectric portion comprises an oxide.

3. The semiconductor device of claim 1 wherein said lower non-monocrystalline semiconductor superlattice portion comprises a plurality of stacked base non-monocrystalline semiconductor monolayers defining an non-monocrystalline base semiconductor portion and at least one non-semiconductor monolayer between adjacent base non-monocrystalline semiconductor portions.

4. The semiconductor device of claim 1 wherein said lateral spacer extends vertically upward from said substrate and along a sidewall of said STI region.

5. The semiconductor device of claim 1 further comprising an oxide layer overlying said superlattice layer.

6. The semiconductor device of claim 1 wherein said base semiconductor comprises silicon.

7. The semiconductor device of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

8. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises oxygen.

9. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon.

10. A method of making a semiconductor device comprising:

forming a shallow trench isolation (STI) region in a semiconductor substrate and extending above a surface thereof;

forming a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers;

each group of layers of the superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer; and

forming a lateral spacer between the superlattice layer and the STI region and comprising a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion.

11. The method of claim 10 wherein the upper dielectric portion comprises an oxide.

12. The method of claim 10 wherein the lower non-monocrystalline semiconductor superlattice portion comprises a plurality of stacked base non-monocrystalline semiconductor monolayers defining an non-monocrystalline base semiconductor portion and at least one non-semiconductor monolayer between adjacent base non-monocrystalline semiconductor portions.

13. The method of claim 10 wherein the lateral spacer extends vertically upward from the substrate and along a sidewall of the STI region.

14. The method of claim 10 further comprising forming an oxide layer overlying the superlattice layer.

15. The method of claim 10 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

16. The method of claim 10 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon.

17. A method of making a semiconductor device comprising:

forming a shallow trench isolation (STI) region in a semiconductor substrate and extending above a surface thereof;

forming a superlattice layer adjacent the surface of the semiconductor substrate and the STI region without using a mask, the superlattice comprising a plurality of stacked groups of layers;

each group of layers of the superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer; and

forming a lateral spacer between the superlattice layer and the STI region.

18. The method of claim 17 wherein forming the lateral spacer comprises forming a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion.

19. The method of claim 18 wherein the upper dielectric portion comprises an oxide.

20. The method of claim 18 wherein the lower non-monocrystalline semiconductor superlattice portion comprises a plurality of stacked base non-monocrystalline semiconductor monolayers defining an non-monocrystalline base semiconductor portion and at least one non-semiconductor monolayer between adjacent base non-monocrystalline semiconductor portions.

21. The method of claim 17 wherein the lateral spacer extends vertically upward from the substrate and along a sidewall of the STI region.

22. The method of claim 17 further comprising forming an oxide layer overlying the superlattice layer.

23. The method of claim 17 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

24. The method of claim 17 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon.