Semiconductor light-emitting device with high light-extraction efficiency

• US 20080258163A1
• Filed: 04/17/2008
• Published: 10/23/2008
• Est. Priority Date: 04/20/2007
• Status: Active Grant

• Current Assignee: Epistar Corporation
• Original Assignee: Huga Optotech Incorporated (Epistar Corporation)
• Inventors: Wang, Wei-Kai, Lin, Su-Hui, Shih, Wen-Chung
• Granted Patent: US 7,956,373 B2
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

The invention discloses a semiconductor light-emitting device and a fabricating method thereof. The semiconductor light-emitting device according to the invention includes a substrate, a multi-layer structure, a top-most layer, and at least one electrode. The multi-layer structure is formed on the substrate and includes a light-emitting region. The top-most layer is formed on the multi-layer structure, and the lower part of the sidewall of the top-most layer exhibits a first surface morphology relative to a first pattern. In addition, the upper part of the sidewall of the top-most layer exhibits a second surface morphology relative to a second pattern. The at least one electrode is formed on the top-most layer. Therefore, the sidewall of the semiconductor light-emitting device according to the invention exhibits a surface morphology, which increases the light-extraction area of the sidewall, and consequently enhances the light-extraction efficiency of the semiconductor light-emitting device.

Claims

1. A method of fabricating a semiconductor light-emitting device, comprising the steps of:

(a) preparing a substrate;

(b) forming a multi-layer structure on the substrate, the multi-layer structure comprising a light-emitting region;

(c) forming a top-most layer on the multi-layer structure;

(d) forming an etching-resistant layer substantially overlaying the top-most layer such that the boundary of the top-most layer is exposed, the boundary of the etching-resistant layer exhibiting a first pattern;

(e) etching the exposed boundary of the top-most layer;

(f) removing the etching-resistant layer; and

(g) forming at least one electrode on the top-most layer and on the multi-layer structure;

wherein the sidewall of the top-most layer exhibits a surface morphology relative to the first pattern.

2. The method of claim 1, between step (e) and step (f), further comprising the steps of:

(e-1) reducing the boundary of the etching-resistant layer such that the boundary of the etching-resistant layer exhibits a second pattern; and

(e-2) etching the exposed boundary of the top-most layer once more;

wherein the surface morphology of the sidewall of the top-most layer relates to the first pattern and the second pattern.

3. The method of claim 1, wherein the top-most layer is formed of Indium-Tin oxide (ITO) or Zinc oxide.

4. The method of claim 1, wherein the light-emitting region comprises one selected from the group consisting of a PN-junction, a double hetero-junction and a multiple quantum well.

5. The method of claim 1, wherein the etching-resistant layer is formed of silicon oxide or a photo-resist material.

6. The method of claim 1, wherein the etching-resistant layer is formed of nickel or aluminum.

7. The method of claim 6, wherein the boundary of the etching-resistant layer with the first pattern is formed by an annealing process.

8. The method of claim 1, wherein the substrate is formed of a material selected from the group consisting of Si, GaN, AlN, sapphire, spinnel, SiC, GaAs, Al₂O₃, LiGaO₂, LiAlO₂, and MgAl₂O₄.

9. The method of claim 1, wherein the sidewall of the substrate exhibits a surface morphology relative to a third pattern.

10. The method of claim 1, wherein the sidewall of the multi-layer structure exhibits a surface morphology relative to a fourth pattern.

11. A semiconductor light-emitting device, comprising:

a substrate;

a multi-layer structure, formed on the substrate, comprising a light-emitting region;

a top-most layer, formed on the multi-layer structure, the lower part of the sidewall of the top-most layer exhibiting a first surface morphology relative to a first pattern; and

at least one electrode, formed on the top-most layer and on the multi-layer structure.

12. The semiconductor light-emitting device of claim 11, wherein the top-most layer is formed of Indium-Tin oxide (ITO) or Zinc oxide.

13. The semiconductor light-emitting device of claim 11, wherein the light-emitting region comprises one selected from the group consisting of a PN-junction, a double hetero-junction and a multiple quantum well.

14. The semiconductor light-emitting device of claim 11, wherein the substrate is formed of a material selected from the group consisting of Si, GaN, AlN, sapphire, spinnel, SiC, GaAs, Al₂O₃, LiGaO₂, LiAlO₂, and MgAl₂O₄.

15. The semiconductor light-emitting device of claim 11, wherein the first surface morphology of the sidewall of the top-most layer is formed by use of an etching-resistant layer whose boundary exhibits the first pattern.

16. The semiconductor light-emitting device of claim 15, wherein the etching-resistant layer is formed of silicon oxide or a photo-resist material.

17. The semiconductor light-emitting device of claim 15, wherein the etching-resistant layer is formed of nickel or aluminum.

18. The semiconductor light-emitting device of claim 17, wherein the boundary of the etching-resistant layer with the first pattern is formed by an annealing process.

19. The semiconductor light-emitting device of claim 17, wherein the upper part of the sidewall of the top-most layer exhibits a second surface morphology relative to a second pattern.

20. The semiconductor light-emitting device of claim 11, wherein the sidewall of the substrate exhibits a surface morphology relative to a third pattern.

21. The semiconductor light-emitting device of claim 11, wherein the sidewall of the multi-layer structure exhibits a surface morphology relative to a fourth pattern.