INSULATED GATE BIPOLAR TRANSISTOR WITH BUILT-IN FREEWHEELING DIODE

• US 20080258172A1
• Filed: 04/08/2008
• Published: 10/23/2008
• Est. Priority Date: 07/24/2003
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Aono, Shinji, TAKAHASHI, Hideki
• Granted Patent: US 7,750,365 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer of a second conductivity type on the second main surface and vertically aligned with a region of the first main electrode in contact with the base region, and a second main electrode formed on the first and second semiconductor layers. An interface between the second main electrode and each of the first and second semiconductor layers is parallel to the first main surface, a distance between the first main surface and the interface is equal to 200 μm or smaller, and a thickness of each of the first and second semiconductor layers is equal to 2 μm or smaller.

Claims

1. An insulated gate bipolar transistor comprising:

a semiconductor substrate of a first conductivity type including a first main surface and a second main surface;

an insulated gate transistor formed in a region of said semiconductor substrate on a side of said semiconductor substrate where said first main surface is included, said insulated gate transistor including a channel of said first conductivity type which is formed within a base region of a second conductivity type during an on state of said insulated gate transistor, said base region extending from said first main surface toward an interior of said semiconductor substrate;

a first main electrode formed on said first main surface and being in contact with said base region of said insulated gate transistor at said first main surface;

a first semiconductor layer of said first conductivity type formed on said second main surface of said semiconductor substrate, facing said insulated gate transistor;

a second semiconductor layer of said second conductivity type formed on said second main surface of said semiconductor substrate, facing said insulated gate transistor, and vertically aligned with a region of the first main electrode in contact with said base region; and

a second main electrode formed on said first semiconductor layer and said second semiconductor layer,

wherein an interface between said second main electrode and each of said first semiconductor layer and said second semiconductor layer is parallel to said first main surface,

a distance between said first main surface and said interface is equal to 200 μ

m or smaller, and

a thickness of each of said first semiconductor layer and said second semiconductor layer is equal to 2 μ

m or smaller.