Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same

• US 20080258206A1
• Filed: 04/17/2007
• Published: 10/23/2008
• Est. Priority Date: 04/17/2007
• Status: Abandoned Application

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Hofmann, Franz
• Application Number:
  US11/736,327
• Publication Number:
  US 20080258206A1
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second gate region is adjacent to the first gate region and extends above a surface of the semiconductor substrate. The second gate region includes a second conductive material.

Claims

1. A method of forming a gate structure, the method comprising:

defining isolation trenches in a semiconductor substrate;

forming columns of a sacrificial material over the semiconductor substrate;

filling the isolation trenches with an insulating material and selectively etching the insulating material with respect to the substrate material at positions lying between adjacent columns of the sacrificial material, thereby forming a recessed structure;

forming a gate oxide on a bottom side and sidewalls of the recessed structure; and

providing a first conductive material in the recessed structure.

2. The method of claim 1, further comprising:

etching the substrate material after etching the insulating material.

3. The method of claim 2, wherein the substrate material is isotropically etched.

4. The method of claim 1, further comprising:

providing a second conductive material over the first conductive material.

5. The method of claim 4, wherein the second conductive material comprises a metal or a metal silicide.

6. The method of claim 1, wherein the first conductive material comprises polysilicon.

7. The method of claim 1, wherein the columns are formed as lines disposed above several adjacent isolation trenches.

8. The method of claim 1, wherein the columns are formed as segments of lines.

9. The method of claim 1, wherein the columns of sacrificial material are formed such that the entire surface of the isolation trenches at positions lying between the columns is uncovered.

10. A method of forming a memory cell array, the method comprising:

forming a plurality of gate structures according to claim 1, wherein adjacent columns of the sacrificial material are used as a guide for selectively etching the insulating material; and

providing wordlines of a second conductive material in contact with the first conductive material.

11. The method of claim 10, wherein the adjacent columns of the sacrificial material are used as a guide for providing the wordlines.

12. The method of claim 10, wherein the wordlines are formed such that an upper surface thereof is disposed beneath a surface of the substrate.

13. The method of claim 10, wherein the wordlines are formed so that an upper surface thereof is disposed above a surface of the substrate.

14. A self-aligned gate structure, comprising:

a first gate region extending in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent the semiconductor substrate portions, the first gate region comprising a first conductive material; and

a second gate region disposed adjacent the first gate region, the second gate region extending above a surface of the semiconductor substrate, the second gate region comprising a second conductive material.

15. The self-aligned gate structure of claim 14, wherein the first gate region does not substantially extend into the semiconductor substrate.

16. The self-aligned gate structure of claim 14, wherein the first gate region extends into the semiconductor substrate to a depth of at least 100 nm.

17. The self-aligned gate structure of claim 14, wherein the first gate region extends into the isolation trenches to a depth of at least 150 nm.

18. The self-aligned gate structure of claim 14, wherein the first conductive material comprises polysilicon.

19. The self-aligned gate structure of claim 14, wherein the second conductive material comprises a metal or a metal silicide.

20. The self-aligned gate structure of claim 14, wherein the first gate region extends into the isolation trenches to a first depth, the first depth being substantially constant in each of the isolation trenches.

21. A memory cell array comprising a plurality of memory cells, each of the memory cells comprising a transistor including a self-aligned gate structure according to claim 14.

22. The memory cell array of claim 21, wherein the second gate region forms part of a wordline.

23. The memory cell array of claim 21, wherein a width of a channel of the transistor is smaller than a width of a source/drain portion of the transistor.

24. An integrated circuit including a self-aligned gate structure according to claim 14.

25. An electronic device comprising an integrated circuit including a self-aligned gate structure according to claim 14.

26. An electronic system comprising the electronic device of claim 25, wherein the electronic system is selected from the group including:

a computer, a server, a router, a game console, a graphics card, a personal digital assistant, a digital camera, a cell phone, an audio system, a video system, and a processing device.

27. A memory cell array, comprising:

active areas and isolation trenches formed in a semiconductor substrate, with FinFETs disposed in the active areas, the active areas being disposed in parallel rows extending in a first direction;

bitlines extending in a second direction different from the first direction, each of the bitlines intersecting a plurality of different rows of active areas; and

wordlines extending in a third direction different from the first and the second directions, respectively, a top surface of a conductive material of the wordlines being disposed above the substrate surface.

28. The memory cell array of claim 27, further comprising capacitors disposed in a regular grid pattern.

29. The memory cell array of claim 27, wherein each of the FinFETs includes a self-aligned gate structure comprising:

a first gate region extending in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions, the first gate region comprising a first conductive material; and

a second gate region disposed adjacent the first gate region, the second gate region extending above a surface of the semiconductor substrate, the second gate region comprising a second conductive material.

30. The memory cell array of claim 27, wherein a width of a channel of the transistor is less than a width of a source/drain portion of the transistor.

31. A method of forming a memory cell array, the method comprising:

defining isolation trenches in a semiconductor substrate;

defining vertical portions of a gate electrode extending in the isolation trenches; and

providing wordlines in contact with corresponding gate electrodes in a self-aligned manner with respect to the gate electrodes.