STRAINED SPACER DESIGN FOR PROTECTING HIGH-K GATE DIELECTRIC

• US 20080258227A1
• Filed: 04/18/2007
• Published: 10/23/2008
• Est. Priority Date: 04/18/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chih-Hao, Chen, Shang-Chih
• Granted Patent: US 7,763,945 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device pair is provided. The semiconductor device pair comprises a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric. A plurality of oxygen-free offset spacer portions are adjacent either side of the respective first and second gate structures, each comprising a stressed dielectric layer, to induce a desired strain on a respective channel region while sealing respective high-K gate dielectric sidewall portions, wherein the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes.

Claims

1. A semiconductor device pair comprising:

a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric; and

a plurality of oxygen-free offset spacer portions adjacent either side of the respective first and second gate structures, each comprising a stressed dielectric layer, to induce a desired strain on a respective channel region while sealing respective high-K gate dielectric sidewall portions, wherein the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes.

2. The semiconductor device pair of claim 1, wherein the offset spacer portions comprise a structure selected from the group consisting of an I-shaped offset spacer only the gate structure sidewalls to minimize a channel strain and an L-shaped spacer covering the gate structure sidewalls and adjacent semiconductor substrate surface portions to maximize a channel strain.

3. The semiconductor device pair of claim 1, wherein the stressed dielectric layer comprises nitrogen element but free of oxygen element.

4. The semiconductor device pair of claim 1, wherein the stressed dielectric layer comprises silicon nitride.

5. The semiconductor device pair of claim 1, further comprising a main spacer formed adjacent to the stressed dielectric layer of the fist gate structure and the second gate structure, wherein the main spacer comprises oxide and nitride layers.

6. The semiconductor device pair of claim 1, wherein the high-K gate dielectric comprises a lowermost interfacial layer formed on the semiconductor substrate.

7. The semiconductor device pair of claim 1, wherein the stressed dielectric layer is tensile or compressive stressed.

8. A semiconductor device, comprising:

a semiconductor substrate comprising an NMOS gate structure and a PMOS gate structure formed thereon, each comprising a high-K gate dielectric; and

a compressive stressed dielectric layer formed over a sidewall of the NMOS gate structure and a PMOS gate structure, wherein the compressive stressed dielectric layer is oxygen-free and seals the high-K gate dielectric edge in the NMOS/PMOS gate structure, the compressive stressed dielectric layer formed over the sidewall of the NMOS gate structure is I-shaped, and the compressive stressed dielectric layer formed over the sidewall of the PMOS gate structure is L-shaped.

9. The semiconductor device of claim 8, wherein the compressive stressed dielectric layer comprises nitrogen element but free of oxygen element.

10. The semiconductor device of claim 8, wherein the compressive stressed dielectric layer comprises silicon nitride.

11. The semiconductor device of claim 8, further comprising a main spacer formed adjacent to the compressive stressed dielectric layer of the NMOS gate structure and the PMOS gate structure, wherein the main spacer comprises oxide and nitride layers.

12. The semiconductor device of claim 8, wherein the high-K gate dielectric comprises a material selected from the group consisting of aluminum-based high-K, hafnium-based high-K, zirconium-based high-K, yttrium-based high-K, lanthanum-based high-K, cerium-based high-K, titanium-based high-K, tantalum-based high-K, stack of these high-K film, or combinations thereof.

13. The semiconductor device of claim 8, wherein the high-K gate dielectric comprises a lowermost interfacial layer formed on the semiconductor substrate.

14. A semiconductor device, comprising:

a semiconductor substrate comprising an NMOS gate structure and a PMOS gate structure formed thereon, each comprising a high-K gate dielectric; and

a tensile stressed dielectric layer formed over a sidewall of the NMOS gate structure and a PMOS gate structure, wherein the tensile stressed dielectric layer is oxygen-free and seals the high-K gate dielectric edge in the NMOS/PMOS gate structure, the tensile stressed dielectric layer formed over the sidewall of the NMOS gate structure is L-shaped, and the tensile stressed dielectric layer formed over the sidewall of the PMOS gate structure is I-shaped.

15. The semiconductor device of claim 14, wherein the tensile stressed dielectric layer comprises nitrogen element but free of oxygen element.

16. The semiconductor device of claim 14, wherein the tensile stressed dielectric layer comprises silicon nitride.

17. The semiconductor device of claim 14, further comprising a main spacer formed adjacent to the tensile stressed dielectric layer of the NMOS gate structure and the PMOS gate structure, wherein the main spacer comprises oxide and nitride layers.

18. The semiconductor device of claim 14, wherein the high-K gate dielectric comprises a material selected from the group consisting of aluminum-based high-K, hafnium-based high-K, zirconium-based high-K, yttrium-based high-K, lanthanum-based high-K, cerium-based high-K, titanium-based high-K, tantalum-based high-K, stack of these high-K film, or combinations thereof.

19. The semiconductor device of claim 14, wherein the high-K gate dielectric comprises a lowermost interfacial layer formed on the semiconductor substrate.