SEMICONDUCTOR DEVICE

• US 20080258258A1
• Filed: 04/16/2008
• Published: 10/23/2008
• Est. Priority Date: 04/20/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamada, Hiroshi, Noma, Takashi, Seki, Yoshinori, Shinogi, Hiroyuki, Ishibe, Shinzo, Uchiyama, Hisayoshi, HORIKOSHI, Katsu
• Granted Patent: US 8,410,577 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a semiconductor integrated circuit formed on a front surface of the semiconductor substrate;

a pad electrode disposed on the front surface so as to be connected to the semiconductor integrated circuit;

a capacitor electrode disposed on a back surface of the semiconductor substrate;

an insulation film disposed on the capacitor electrode; and

a wiring layer disposed on the insulation film and connected to the pad electrode,

wherein the capacitor electrode, the insulation film and the wiring layer are configured to form a capacitor.

2. The semiconductor device of claim 1, wherein the capacitor electrode, the insulation film and the wiring layer extend from the back surface of the semiconductor substrate to a side surface of the semiconductor substrate so that the extended portions of the capacitor electrode, the insulation film and the wiring layer form an additional capacitance to the capacitor.

3. The semiconductor device of claim 1, wherein the semiconductor substrate has a via hole penetrating the semiconductor substrate, and the insulation film and the wiring layer extend from the back surface of the semiconductor substrate into the via hole.

4. The semiconductor device of claim 1, further comprising a first conductive terminal disposed on the back surface of the semiconductor substrate and connected to the pad electrode through the wiring layer and a second conductive terminal disposed on the back surface of the semiconductor substrate and in contact with the capacitor electrode.

5. The semiconductor device of claim 1, further comprising a supporting body attached to the semiconductor substrate.

6. The semiconductor device of claim 1, wherein the capacitor electrode and the semiconductor substrate are configured to receive a reference voltage.