INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING

• US 20080258289A1
• Filed: 03/27/2008
• Published: 10/23/2008
• Est. Priority Date: 04/23/2007
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Chow, Seng Guan, Pendse, Rajendra D., Shim, Il Kwon, Carson, Flynn
• Granted Patent: US 8,409,920 B2
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

An integrated circuit package system comprising: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.

Claims

1. An integrated circuit package system comprising:

forming an area array substrate;

mounting surface conductors on the area array substrate;

forming a molded package body on the area array substrate and the surface conductors;

providing a step in the molded package body; and

exposing a surface conductor by the step.

2. The system as claimed in claim 1 further comprising coupling an area array device to the surface conductors.

3. The system as claimed in claim 1 wherein forming the molded package body includes:

electrically connecting a first integrated circuit to the area array substrate;

positioning a second integrated circuit over the first integrated circuit; and

injecting a molding compound on the substrate, the surface conductors, the first integrated circuit, and the second integrated circuit.

4. The system as claimed in claim 1 wherein exposing the surface conductor includes:

forming contact pads on the area array substrate for mounting the surface conductors;

forming system contacts on the opposing side of the area array substrate; and

coupling a via between the contact pad and the system contact.

5. The system as claimed in claim 1 wherein providing the step in the molded package body includes:

forming a core section of the molded package body; and

reducing a step height from the core section for forming a region surrounding the core section being coplanar to the area array substrate including exposing the surface conductors.

6. An integrated circuit package system comprising:

forming an area array substrate having a component side and a system side;

mounting surface conductors on the area array substrate including pressing a solder ball;

forming a molded package body on the area array substrate and the surface conductors including a core section;

providing a step in the molded package body including reducing a step height from the core section for forming a region surrounding the core section being coplanar to the area array substrate; and

exposing a surface conductor by the step for reducing a package height of a package stack.

7. The system as claimed in claim 6 further comprising coupling an area array device to the surface conductors including coupling a flip chip integrated circuit, a ball grid array package, or an interposer.

8. The system as claimed in claim 6 wherein forming the molded package body includes:

electrically connecting a first integrated circuit to the area array substrate including coupling an electrical interconnect between the first integrated circuit and the substrate;

positioning a second integrated circuit over the first integrated circuit including applying a second adhesive; and

injecting a molding compound on the area array substrate, the surface conductors, the first integrated circuit, the second integrated circuit, and the electrical interconnect.

9. The system as claimed in claim 6 wherein exposing the surface conductor includes:

providing the area array substrate under the molded package body including providing a laminate glass epoxy substrate, a ceramic substrate, or a flexible tape substrate;

mounting a flip chip integrated circuit on the area array substrate including coupling a contact pad to the flip chip integrated circuit;

coupling a via to the contact pad; and

coupling a system contact to the via.

10. The system as claimed in claim 6 further comprising:

coupling an embedded chip to the area array substrate;

mounting a chip interconnect to the active side of the embedded chip including coupling a third external chip over the core section; and

wherein;

reducing the step height from the core section for exposing the surface conductors including mounting a first area array device and a second area array device.

11. An integrated circuit package system comprising:

an area array substrate;

surface conductors mounted on the area array substrate; and

a molded package body, having a step, on the area array substrate and the surface conductors includes the surface conductors exposed by the step.

12. The system as claimed in claim 11 further comprising an area array device coupled to the surface conductors.

13. The system as claimed in claim 11 wherein the molded package body includes:

a first integrated circuit electrically connected to the area array substrate;

a second integrated circuit over the first integrated circuit; and

a molding compound on the area array substrate, the surface conductors, the first integrated circuit, and the second integrated circuit.

14. The system as claimed in claim 11 wherein the surface conductor exposed includes:

contact pads, on the area array substrate, with the surface conductor mounted thereon;

system contacts on the opposing side of the area array substrate; and

vias between the contact pads and the system contacts.

15. The system as claimed in claim 11 wherein the molded package body having the step includes:

a core section of the molded package body; and

a step height reduced from the core section includes a region around the core section that is coplanar to the area array substrate with the surface conductors exposed.

16. The system as claimed in claim 11 further comprising:

a component side and a system side on the area array substrate;

a solder ball, pressed, on the area array substrate;

a core section in the molded package body;

a step height reduced from the core section includes a region around the core section that is coplanar to the area array substrate; and

a package height of a package stack reduced by the step height.

17. The system as claimed in claim 16 further comprising an area array device coupled to the surface conductors includes a flip chip integrated circuit, a ball grid array package, or an interposer.

18. The system as claimed in claim 16 wherein the molded package body includes:

a first integrated circuit electrically connected to the area array substrate includes an electrical interconnect coupled between the first integrated circuit and the area array substrate;

a second integrated circuit over the first integrated circuit includes a second adhesive applied; and

a molding compound on the area array substrate, the surface conductors, the first integrated circuit, the second integrated circuit, and the electrical interconnect.

19. The system as claimed in claim 16 wherein the surface conductor exposed includes:

a laminate glass epoxy substrate, a ceramic substrate, or a flexible tape substrate as the area array substrate;

a flip chip integrated circuit on the area array substrate includes a contact pad coupled to the flip chip integrated circuit;

a via coupled to the contact pad; and

a system contact coupled to the via.

20. The system as claimed in claim 16 further comprising:

an embedded chip coupled to the area array substrate;

a chip interconnect mounted to the active side of the embedded chip includes a third external chip coupled over the core section; and

a first area array device and a second area array device mounted on the surface conductors.