Semiconductor Packaging With Internal Wiring Bus

• US 20080258291A1
• Filed: 04/17/2008
• Published: 10/23/2008
• Est. Priority Date: 04/19/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Wu, Albert, Liou, Shiann-Ming, Liu, Chenglin
• Granted Patent: US 7,911,053 B2
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48111 the wire connector extending above another semiconductor or solid-state body
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence

Abstract

A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies.

Claims

1. A packaged semiconductor, comprising:

inner bond fingers;

at least first and second semiconductor dies;

an interposer;

wiring between said first and second semiconductor dies and said inner bond fingers;

wiring between said interposer and said inner bond fingers; and

wiring between said interposer and said first and second semiconductor dies.

2. A packaged semiconductor according to claim 1, wherein said first and second semiconductor dies are positioned opposite each other such that said first semiconductor die prevents said second semiconductor die from having full direct access to said inner bond fingers and said second semiconductor die prevents said first semiconductor die from having full direct access to said inner bond fingers, and wherein wiring between said interposer and said first and second semiconductor dies provides indirect access to said inner bond fingers.

3. A packaged semiconductor according to claim 1, wherein said first and second semiconductor dies are stacked on top of each other.

4. A packaged semiconductor according to claim 1, wherein said first and second semiconductor dies are positioned side-by-side.

5. A packaged semiconductor according to claim 1, wherein said interposer is stacked on top of either said first or second semiconductor dies.

6. A packaged semiconductor according to claim 1, wherein said first or second semiconductor die is stacked on top of said interposer.

7. A packaged semiconductor according to claim 1, wherein said interposer is positioned side-by-side of said first and second semiconductor dies.

8. A packaged semiconductor according to claim 1, wherein said interposer is positioned between said first and second semiconductor dies.

9. A packaged semiconductor according to claim 1, wherein said interposer functions as a capacitor or an inductor.

10. A packaged semiconductor according to claim 1, comprising:

a plurality of interposers; and

a plurality of semiconductor dies,

wherein each of the plurality of interposers is positioned side-by-side with each of the other plurality of interposers, and

wherein each of the plurality of semiconductor dies is stacked on top of each of the plurality of interposers.

11. A packaged semiconductor according to claim 10, wherein each of said plurality of interposers is positioned between each of said plurality of semiconductor dies.

12. A packaged semiconductor according to claim 1, wherein said interposer is either a BGA substrate material or Silicon die with simple metallization.

13. A packaged semiconductor according to claim 1, further comprising a die pad, wherein said first and second semiconductor dies and said interposer are connected to said die pad.

14. A packaged semiconductor according to claim 13, wherein said die pad is exposed for providing thermal regulation.

15. A packaged semiconductor according to claim 1, wherein said interposer comprises:

a first set of ground and power connections; and

a second set of ground and power connections,

wherein said first set of ground and power connections are routed to said second set of ground and power connections,

wherein said inner bond fingers are wire bonded to said first set of ground and power connections, and

wherein said first and second semiconductor dies are wire bonded to said second set of ground and power connections.

16. A method for manufacturing a semiconductor package, comprising:

mounting an interposer on a surface of a die pad;

mounting first and second semiconductor dies on said surface of said die pad;

connecting inner bond fingers and said first and second semiconductor dies with wiring;

connecting said interposer and said inner bond fingers with wiring; and

connecting said interposer and said first and second semiconductor dies with wiring.

17. A method for manufacturing a semiconductor package according to claim 16, wherein said first and second semiconductor dies are positioned opposite each other such that said first semiconductor die prevents said second semiconductor die from having full direct access to said inner bond fingers and said second semiconductor die prevents said first semiconductor die from having full direct access to said inner bond fingers, and wherein wiring between said interposer and said first and second semiconductor dies provides indirect access to said inner bond fingers.

18. A method for manufacturing a semiconductor package according to claim 16, wherein said first semiconductor die is mounted to said die pad and said second semiconductor die is mounted to said first semiconductor so that said first and second semiconductor dies are stacked on top of each other.

19. A method for manufacturing a semiconductor package according to claim 16, wherein said first and second semiconductor die are mounted to said die pad side-by-side.

20. A method for manufacturing a semiconductor package according to claim 16, wherein said interposer is mounted to either said first or second semiconductor die so that said interposer is stacked on top of either said first or second semiconductor die.

21. A method for manufacturing a semiconductor package according to claim 16, wherein said first or second semiconductor die is mounted to said interposer so that said first or second semiconductor die is stacked on top of said interposer.

22. A method for manufacturing a semiconductor package according to claim 16, wherein said interposer is mounted to said die pad side-by-side with said first and second semiconductor dies.

23. A method for manufacturing a semiconductor package according to claim 16, wherein said interposer is mounted to said die pad between said first and second semiconductor dies.

24. A method for manufacturing a semiconductor package according to claim 16, further comprising:

mounting a plurality of interposers to said die pad; and

mounting each of a plurality of semiconductor dies to each of said plurality of interposers,

wherein said plurality of interposers are mounted to said die pad so that they are positioned side-by-side, and

wherein each of said plurality of semiconductor dies are mounted to each of said plurality of interposers so that said plurality of semiconductor dies are stacked on top of said plurality of interposers.

25. A method for manufacturing a semiconductor package according to claim 24, wherein each of said plurality of interposers is positioned between each of said plurality of semiconductor dies.

26. A method for manufacturing a semiconductor package according to claim 16, wherein said interposer is either a BGA substrate material or Silicon die with simple metallization.

27. A method for manufacturing a semiconductor package according to claim 16, wherein said die pad is exposed for providing thermal regulation.

28. A method for manufacturing a semiconductor package according to claim 16, further comprising:

connecting a first set of ground and power connections to said interposer;

connecting a second set of ground and power connections to said interposer;

routing said first set of ground and power connections to said second set of ground and power connections;

bonding said inner bond fingers to said first set of ground and power connections; and

bonding said first and second semiconductor dies to said second set of ground and power connections.