Semiconductor Device and Method for Fabricating the Same

• US 20080258306A1
• Filed: 04/18/2008
• Published: 10/23/2008
• Est. Priority Date: 04/19/2007
• Status: Abandoned Application

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Huang, Chih-Ming, Huang, Chien-Ping, Hsiao, Cheng-Hsu, Chang, Chin-Huang, Chiang, Cheng-Chia
• Application Number:
  US12/105,538
• Publication Number:
  US 20080258306A1
• Time in Patent Office: Days
• US Class Current: 257/762
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.

Claims

1. A method for fabricating semiconductor devices, comprising the steps of:

providing a wafer comprising a plurality of chips, each of the wafer and the chips having an active surface and an opposing non-active surface, and the active surface of each of the chips being formed with a plurality of bond pads thereon, and after each of the chips is determined to be a good die by a chip probing (CP) process, forming a first metal layer on any adjacent two of the chips to electrically connect the bond pads of the adjacent chips to each other;

performing a singulation process on the wafer to separate the chips, and mounting the chips on a surface of a carrier having a plurality of conductive traces disposed on the surface in a manner that gaps are formed between the adjacent chips, with a portion of the conductive traces being exposed from the gaps;

forming a dielectric layer in the gaps, and forming a plurality of openings in the dielectric layer to expose the portion of the conductive traces;

forming a resist layer over the chips and the dielectric layer, and forming a plurality of openings in the resist layer to expose the first metal layers on the chips and the openings of the dielectric layer;

forming a plurality of second metal layers in the openings of the dielectric layer and in the openings of the resist layer, so as to allow the bond pads on the chips to be electrically connected to the conductive traces on the carrier by the first and second metal layers; and

removing the resist layer, performing a singulation process along the dielectric layer between the chips, and removing the carrier, so as to separate the chips and allow the conductive traces to be exposed on the non-active surfaces of the chips, thereby forming the semiconductor devices.

2. The method of claim 1, wherein the carrier is a metal board, and the conductive traces are formed on the surface of the carrier by electroplating and are made of gold/nickel/gold (Au/Ni/Au).

3. The method of claim 1, wherein the first metal layer is an under bump metallurgy (UBM) layer formed on the active surface of each of the chips by means of a redistribution layer (RDL) technique and is electrically connected to the bond pads of the adjacent chips, and the wafer is thinned, and the singulated chips are determined to be the good dies before they are mounted on the carrier.

4. The method of claim 1, wherein the chips are mounted on the carrier by an adhesive layer formed between the chips and the carrier.

5. The method of claim 1, wherein the dielectric layer is made of epoxy resin or polyimide, and the resist layer is a dry film.

6. The method of claim 1, wherein the openings of the dielectric layer are formed by laser or etching, and the openings of the dielectric layer are spaced apart from sides of the chips such that the sides of the chips are covered by the dielectric layer.

7. The method of claim 1, wherein the second metal layers comprise a copper (Cu) layer, a nickel (Ni) layer and a solder material layer, wherein an electroplating process is performed to deposit the copper layer in the openings of the dielectric layer and over the first metal layers and the dielectric layer, deposit the nickel layer on the copper layer, and deposit the solder material layer on the nickel layer.

8. The method of claim 1, wherein the second metal layers on the active surface of the chip of one of the semiconductor devices are electrically connected to the conductive traces on the non-active surface of the chip of another one of the semiconductor devices by a thermal compression process, so as to form a multi-chip stacked structure.

9. The method of claim 8, wherein a gap between the two semiconductor devices in the multi-chip stacked structure is filled with an underfill material.

10. The method of claim 1, further comprising after forming the second metal layers and removing the resist layer and before performing the singulation process along the dielectric layer and removing the carrier, forming an insulating layer on the active surfaces of the chips and the second metal layers.

11. The method of claim 10, wherein a plurality of conductive elements are disposed on outer surfaces of the conductive traces on the non-active surfaces of the chips.

12. The method of claim 11, wherein a plurality of openings are formed in the insulating layer to expose the second metal layers, so as to allow the exposed second metal layers to be electrically connected to the conductive elements disposed on the conductive traces in another one of the semiconductor devices.

13. The method of claim 1, wherein the first metal layers have extending portions extended through the bond pads and towards centers of the chips, and a plurality of extension pads are formed at ends of the extending portions of the first metal layers.

14. The method of claim 13, wherein the extension pads are exposed from the openings of the resist layer, and the second metal layers are formed in the openings of the dielectric layer and on the first metal layers and the extension pads exposed from the openings of the resist layer.

15. The method of claim 14, wherein an insulating layer is formed on the active surfaces of the chips and the second metal layers, a plurality of openings are formed in the insulating layer in positions corresponding to the extension pads to expose the second metal layers on the extension pads so as to allow electronic elements to be mounted on the exposed second metal layers, and a plurality of conductive elements are disposed on the conductive traces on the non-active surfaces of the chips.

16. A semiconductor device, comprising:

a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface of the chip, and first metal layers are formed on the bond pads and to edges of the active surface of the chip;

conductive traces disposed on the non-active surface of the chip;

a dielectric layer covering sides of the chip and formed with openings therein for exposing a portion of the conductive traces; and

a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, so as to allow the bond pads on the chip to be electrically connected to the conductive traces by the first and second metal layers.

17. The semiconductor device of claim 16, further comprising an adhesive layer formed between the non-active surface of the chip and the conductive traces, wherein the conductive traces are disposed in positions corresponding to edges of the adhesive layer.

18. The semiconductor device of claim 16, wherein the conductive traces are made of gold/nickel/gold (Au/Ni/Au), the dielectric layer is made of epoxy resin or polyimide, and the second metal layers comprise a copper (Cu) layer, a nickel (Ni) layer on the copper layer, and a solder material layer on the nickel layer.

19. The semiconductor device of claim 16, wherein the openings of the dielectric layer are spaced apart from the sides of the chip, such that the sides of the chip are covered by the dielectric layer.

20. The semiconductor device of claim 16, wherein the second metal layers on the active surface of the chip of the semiconductor device are electrically connected to the conductive traces disposed on the non-active surface of the chip of another semiconductor device in a multi-chip stacked structure.

21. The semiconductor device of claim 20, wherein a gap between the two semiconductor devices in the multi-chip stacked structure is filled with an underfill material.

22. The semiconductor device of claim 16, further comprising an insulating layer formed on the active surface of the chip and the second metal layers.

23. The semiconductor device of claim 22, further comprising a plurality of conductive elements disposed on outer surfaces of the conductive traces on the non-active surface of the chip.

24. The semiconductor device of claim 23, wherein a plurality of openings are formed in the insulating layer to expose the second metal layers, so as to allow the exposed second metal layers to be electrically connected to the conductive elements disposed on the conductive traces of the another semiconductor device.

25. The semiconductor device of claim 16, wherein each of the first metal layers is an under bump metallurgy (UBM) layer formed by a redistribution layer (RDL), and the chip is thinned and determined to be a good die.

26. The semiconductor device of claim 16, wherein the first metal layers have extending portions extended through the bond pads and towards a center of the chip, and a plurality of extension pads are formed at ends of the extending portions of the first metal layers.

27. The semiconductor device of claim 26, wherein the second metal layers are formed on the extension pads.

28. The semiconductor device of claim 27, further comprising an insulating layer formed over the active surface of the chip and the second metal layers, wherein a plurality of openings are formed in the insulating layer in positions corresponding to the extension pads to expose the second metal layers on the extension pads so as to allow electronic elements to be mounted on the exposed second metal layers, and a plurality of conductive elements are disposed on the conductive traces on the non-active surface of the chip.