Digital Component Deterministic Pseudo Random Clock and Noise Source Device Based on a Random Frequency Modulated Oscillator

• US 20080258825A1
• Filed: 05/25/2006
• Published: 10/23/2008
• Est. Priority Date: 10/27/2005
• Status: Active Grant

• Current Assignee: Fortress GB Limited
• Original Assignee: Fortress GB Limited
• Inventors: Hecht, Avi, Granot, Ran, Gressel, Carmi David
• Granted Patent: US 7,852,162 B2
• Time in Patent Office: Days
• US Class Current: 331/78
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

Random number generators are used for entertainment in gambling, lotteries and video gaming devices. True Random Number Generators, as are now currently defined, must be actuated by a physical noise source, typically based on the uncertainty of the phase differences of a stable and an unstable autonomous oscillator. In this invention an autonomous random frequency modulated oscillator driven by a self contained pseudo-random number generator outputs three loosely correlated random binary streams. Included in the invention is a hardware method for proving wandering phase differences and also the existence of a colored random distribution of concatenated nibbles.

Claims

1-19. -19. (canceled)

20. A method for ascertaining operation of a metastable oscillator operating in conjunction with a host which supplies a sampling clock, the method comprising:

counting a number of pulses generated by said oscillator which occur within each of a first sequence of time intervals; and

generating an oscillator operation check output which indicates whether or not the number of pulses occurring within a second sequence of time intervals, varies.

36. A method according to claim 20 wherein said time intervals are of a fixed length, the fixed length being an integer multiple of half of the period of the sampling clock.

37. A method according to claim 20 wherein said first and second sequences of time intervals are identical.

21. Noise source apparatus operative in conjunction with host apparatus generating, at intervals, a sampling clock which samples at least one output variable at a host sampling frequency, the apparatus comprising:

a. a randomly activated deterministic pseudorandom number generating device operative to generate a first plurality of randomized binary streams;

b. a frequency modulated oscillator operating at a second plurality of binary metastable frequency levels, at least some of which are uncorrelated to the sampling clock, the oscillator being operative to activate the pseudorandom number generating device;

c. a frequency modulator circuit which is controlled by the pseudorandom number generating device and which generates oscillator input signals which define random intervals in the course of which the oscillator switches between its second plurality of binary frequency levels; and

d. an encoding-sampling device receiving, encoding and sampling, in accordance with the sampling clock, the first plurality of randomized binary streams, thereby to generate at least one encoded sampled output, and feeding back an intermediate fed-back signal to the randomly activated deterministic pseudo-random number generating device.

22. Apparatus according to claim 21 wherein the encoding-sampling device comprises a double-encoding double-sampling device receiving, double-encoding and double-sampling the first plurality of randomized binary streams.

23. Apparatus according to claim 22 wherein said double-encoding double-sampling device comprises digital logic and an array of buffers serving said digital logic operative to encode, debias and sample and then re-encode, re-debias and re-sample said first plurality of randomized binary streams.

24. Apparatus according to claim 21 wherein said first plurality of streams are encoded and complemented by an output of said oscillator, are further encoded, and are again sampled by said sampling clock and are output to activate permutations in the deterministic pseudorandom number generator.

25. Apparatus according to claim 21 wherein said oscillator is operative to debias samples within the first plurality of randomized binary streams before said samples are encoded by the encoding-sampling device.

26. Apparatus according to claim 21 wherein said oscillator is operative to debias samples within the first plurality of randomized binary streams after said samples are encoded by the encoding-sampling device.

27. Noise source apparatus according to claim 21 wherein:

said frequency modulated oscillator has a metastable output and is operative to generate at least two random frequency modulated levels of at least one at least almost unbiased random frequency modulated signal; and

said frequency modulator circuit is operative;

to control the at least two random frequency modulated levels of the at least one at least almost unbiased signal by generating oscillator modulating signals, and

to receive from the oscillator, and encode, said at least one at least almost unbiased random frequency modulated signal, thereby to generate at least one output variable which comprises an encoded form of said at least one at least almost unbiased random signal for sampling by the host apparatus,

said noise source apparatus also comprising at least one logic circuit with at least one binary output operative to randomly operate upon a random frequency modulator circuit.

28. Apparatus according to claim 21 wherein each of said second plurality of binary metastable frequency levels is in a range of from less than two to at least 150 times higher than the host sampling frequency.

29. Apparatus according to claim 24 and also comprising at least one delay circuit operative to generate at least one delayed signal by phase shifting at least one of said encoded complemented and further encoded plurality of streams thereby increasing phase difference between said oscillator output, said at least one delayed signal and said sampling clock.

30. Apparatus according to claim 21 and also comprising missed signal clock apparatus comprising:

a. a metastable clock generating an at least almost unbiased metastable clock output;

b. a first digitized logic circuit driven by said metastable clock output which generates a first random binary string comprising at least one encoded binary signal with an approximate probability of one half;

c. a second digitized logic circuit driven by said metastable clock output which generates a second random binary string comprising a sequence of lone zeroes each followed by a set of at least two consecutive binary ones, wherein said sequence of sets of at least two ones comprises sets of exactly two ones randomly interspersed with sets of more than two ones; and

d. synchronization circuitry operative to combine said first and second random binary strings by outputting a combined output string including a binary one at a given position in the combined output string if at least one of the elements in the same given positions within said first and second binary strings is a one; and

outputting a zero if both of the elements in the same given positions within said first and second binary strings are in a zero state, such that said combined output string comprises more than two-thirds of binary ones, and so as to synchronize said combined output string to said sampling clock.

31. Apparatus according to claim 21 wherein the frequency modulator circuit is operative to generate switch-shunting control signals and wherein said frequency modulated oscillator has an instantaneous frequency and comprises an odd number of concatenated logic inverters defining an instantaneous propagation interval, at least some of which are randomly switch-shunted by said control signals, thereby lowering said instantaneous propagation interval and increasing the instantaneous frequency of said frequency modulated oscillator.

32. Apparatus according to claim 21 wherein the frequency modulated oscillator has an instantaneous frequency and comprises:

a logic inverter; and

a plurality of concatenated delay circuits, connected in a ring and defining a total propagation time of a binary signal traveling through the ring, wherein said ring is closed at one point by said logic inverter,

wherein at least one of said plurality of concatenated delay circuits is switch shunted thereby to reduce said total propagation time and to increase the instantaneous frequency of said frequency modulated oscillator.

33. Apparatus according to claim 21 wherein the frequency modulated oscillator comprises:

a digital to analog circuit emitting a first voltage at least if all of said oscillator input signals are at logic zero and emitting a second voltage at least if all of said oscillator input signals are at logic one; and

a voltage to frequency converter generating metastable outputs which are a function of at least said oscillator input signals.

34. Apparatus according to claim 27 wherein said metastable output has a frequency in a range of from less than two to at least 150 times higher than the host sampling frequency.

35. Apparatus according to claim 21 wherein said encoding-sampling device is operative to generate at least one AIS 31 compliant output stream uncorrelated to said host-supplied sampling clock.

38. Noise source apparatus operative in conjunction with host apparatus which at intervals generates a signal to sample at least one output variable at a host sampling frequency;

the apparatus comprising;

a. a frequency modulated oscillator operating at a plurality of levels of frequency and having a metastable output frequency, the oscillator being operative to generate at least one at least almost unbiased signal;

b. a frequency modulator circuit operative;

to control the plurality of levels of frequency of the frequency modulated oscillator by generating oscillator input signals, and

to receive from the oscillator, and to encode, said at least one at least almost unbiased signal, thereby to generate at least one output variable which comprises an encoded form of said at least one at least almost unbiased signal, for sampling by the host apparatus; and

c. at least one logic circuit with at least one binary output operative to randomly operate upon a random frequency modulator circuit.

39. Apparatus according to claim 38 wherein said metastable output frequency is in a range of from less than two to at least 150 times higher than the host sampling frequency.

40. Missed signal clock apparatus operative in conjunction with a host sampling device having a host clock, the apparatus comprising:

a. a metastable clock generating an at least almost unbiased metastable clock output;

b. a first digitized logic circuit driven by said metastable clock output which generates a first random binary string comprising at least one encoded binary signal with an approximate probability of one half;

c. a second digitized logic circuit driven by said metastable clock output which generates a second random binary string comprising a sequence of lone zeroes each followed by a set of at least two consecutive binary ones, wherein said sequence of sets of at least two ones comprises sets of exactly two ones randomly interspersed with sets of more than two ones; and

d. synchronization circuitry operative to combine said first and second random binary strings by outputting a binary one if at least one of the corresponding elements of the binary strings is a one; and

outputting a zero if both of the corresponding elements of the binary strings are in a zero state, thereby to generate a combined output comprising more than two-thirds of binary ones, and to synchronize said combined output to said host clock.

41. Apparatus for ascertaining operation of a metastable oscillator operating in conjunction with a host which supplies a sampling clock, the apparatus comprising:

a pulse-per-interval counter operative to count a number of pulses generated by said oscillator which occur within each of a first sequence of time intervals; and

an oscillator operation verifier operative to generate an oscillator operation check output which indicates whether or not the number of pulses occurring within a second sequence of time intervals, varies.

42. A noise generating method operative in conjunction with host apparatus which at intervals generates a signal to sample at least one output variable at a host sampling frequency;

the method comprising;

using a frequency modulated oscillator operating at a plurality of levels of frequency and having a metastable output frequency to generate at least one at least almost unbiased signal;

using a frequency modulator circuit to control the plurality of levels of frequency of the frequency modulated oscillator by generating oscillator input signals, and to receive therefrom, and encode, said at least one at least almost unbiased signal, thereby to generate at least one output variable which comprises an encoded form of said at least one at least almost unbiased signal, for sampling by the host apparatus; and

using at least one logic circuit with at least one binary output to randomly operate upon a random frequency modulator circuit.

43. A noise generating method operative in conjunction with host apparatus comprising a host supplied sampling clock which at intervals generates a signal to sample at least one output variable at a host sampling frequency, the method comprising:

using a randomly activated deterministic pseudorandom number generating device operative to generate a first plurality of randomized binary streams;

operating a frequency modulated oscillator operating at a second plurality of binary metastable frequency levels, at least some of which are uncorrelated to the host supplied sampling clock and using the oscillator to activate the pseudorandom number generating device;

controlling a frequency modulator circuit using the pseudorandom number generating device and generating oscillator input signals which define random intervals in the course of which the oscillator switches between its second plurality of binary frequency levels; and

receiving, encoding and sampling, in accordance with the host supplied sampling clock, the first plurality of randomized binary streams, thereby to generate an encoded sampled output and feeding back an intermediate fed-back signal to the randomly activated deterministic pseudo-random number generating device.

44. A method for clocking missed signals operative in conjunction with a host sampling device having a host clock, the method comprising:

generating an at least almost unbiased metastable clock output;

using a first digitized logic circuit driven by said metastable clock output, generating a first random binary string comprising at least one encoded binary signal with an approximate probability of one half;

using a second digitized logic circuit driven by said metastable clock output, generating a second random binary string comprising a sequence of lone zeroes each followed by a set of at least two consecutive binary ones, wherein said sequence of sets of at least two ones comprises sets of exactly two ones randomly interspersed with sets of more than two ones; and

,

combining said first and second random binary strings by outputting a binary one if at least one of the corresponding elements of the binary strings is a one; and

outputting a zero if both of the corresponding elements of the binary strings are in a zero state, thereby to generate a combined output comprising more than two-thirds of binary ones, and to synchronize said combined output to said host clock.