Integrating/SAR ADC and method with low integrator swing and low complexity
First Claim
1. Reconfigurable circuitry in a hybrid delta-sigma/SAR ADC (analog-to-digital) circuit for converting an input voltage to a digital result, the reconfigurable circuitry comprising:
- (a) an integrator including(1) an amplifier,(2) a plurality of input capacitors and first and second integrating capacitors, and(3) a plurality of switches for selectively coupling the plurality of input capacitors and the first and second integrating capacitors between various terminals of the amplifier and input terminals of the integrator to effectuate operation of the hybrid delta-sigma/SAR ADC in delta-sigma ADC and SAR ADC modes thereof;
(b) a comparator having an input coupled to an output of the integrator, an output of the comparator being coupled to MSB/LSB combination logic of the hybrid delta-sigma/SAR ADC circuit;
(c) digital control circuitry coupled to control electrodes of the plurality of switches for controlling the plurality of switches by performing a plurality of cycles of SAR ADC operation for generating each of one or a plurality of SAR bits; and
(d) the digital control circuitry creating an entire reference voltage value equal to the sum of a first voltage and a second voltage, a first cycle including multiplying a residue voltage of the integrator by 2, a second cycle integrating the second voltage in a first direction by means of the integrator if the comparator changes state or in a second direction opposite to the first direction if the comparator does not change state, and a third cycle integrating the first voltage in a direction that causes the integrator output voltage to equal either 2×
Vresidue−
Vref or 2×
Vresidue+Vref, wherein Vresidue is a residue voltage which is an output voltage of the integrator at the end of a preceding cycle and Vref is equal to the entire reference voltage value.
1 Assignment
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Accused Products
Abstract
A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (ΔVbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (ΔVbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue−Vref or 2×Vresidue+Vref.
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Citations
21 Claims
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1. Reconfigurable circuitry in a hybrid delta-sigma/SAR ADC (analog-to-digital) circuit for converting an input voltage to a digital result, the reconfigurable circuitry comprising:
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(a) an integrator including (1) an amplifier, (2) a plurality of input capacitors and first and second integrating capacitors, and (3) a plurality of switches for selectively coupling the plurality of input capacitors and the first and second integrating capacitors between various terminals of the amplifier and input terminals of the integrator to effectuate operation of the hybrid delta-sigma/SAR ADC in delta-sigma ADC and SAR ADC modes thereof; (b) a comparator having an input coupled to an output of the integrator, an output of the comparator being coupled to MSB/LSB combination logic of the hybrid delta-sigma/SAR ADC circuit; (c) digital control circuitry coupled to control electrodes of the plurality of switches for controlling the plurality of switches by performing a plurality of cycles of SAR ADC operation for generating each of one or a plurality of SAR bits; and (d) the digital control circuitry creating an entire reference voltage value equal to the sum of a first voltage and a second voltage, a first cycle including multiplying a residue voltage of the integrator by 2, a second cycle integrating the second voltage in a first direction by means of the integrator if the comparator changes state or in a second direction opposite to the first direction if the comparator does not change state, and a third cycle integrating the first voltage in a direction that causes the integrator output voltage to equal either 2×
Vresidue−
Vref or 2×
Vresidue+Vref, wherein Vresidue is a residue voltage which is an output voltage of the integrator at the end of a preceding cycle and Vref is equal to the entire reference voltage value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 19, 20)
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16. A method of operating reconfigurable circuitry in a hybrid delta-sigma/SAR ADC (analog-to-digital converter),
the reconfigurable circuitry including an integrator including an amplifier, a plurality of input capacitors, first and second integrating capacitors, a plurality of switches for selectively coupling the plurality of input capacitors and the first and second integrating capacitors to various terminals of the amplifier and input terminals of the integrator to effectuate operation of the hybrid delta-sigma/SAR ADC in delta-sigma ADC and SAR ADC modes thereof, and a comparator coupled to an output voltage of the integrator, the method comprising: -
(a) controlling the plurality of switches by performing a plurality of cycles of SAR operation of the hybrid delta-sigma/SAR ADC for generating each of a plurality of SAR bits, the controlling in effect creating an entire reference voltage value equal to the sum of a first voltage and a second voltage; (b) performing a first cycle by multiplying a residue voltage of the integrator by 2; (c) performing a second cycle by integrating the second voltage in a first direction by means of the integrator if the comparator changes state or in a second direction opposite to the first direction if the comparator does not change state; and (d) performing a third cycle by integrating the first voltage in a direction that causes the output voltage of the integrator to equal either 2×
Vresidue−
Vref or 2×
Vresidue+Vref, wherein Vresidue is a residue voltage which is an output voltage of the integrator at the end of a preceding cycle and Vref is equal to the entire reference voltage value. - View Dependent Claims (17, 18)
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21. Reconfigurable circuitry in a hybrid delta-sigma/SAR ADC (analog-to-digital converter), comprising:
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(a) integrating means including an amplifier, a plurality of input capacitors, first and second integrating capacitors, a plurality of switches for selectively coupling the plurality of input capacitors and the first and second integrating capacitors to various terminals of the amplifier and input terminals of the integrator to effectuate operation of the hybrid delta-sigma/SAR ADC in delta-sigma ADC and SAR ADC modes thereof, and a comparator coupled to an output voltage of the integrator; (b) means for controlling the plurality of switches by performing a plurality of cycles of SAR operation of the hybrid delta-sigma/SAR ADC for generating each of a plurality of SAR bits, the controlling in effect creating an entire reference voltage value equal to the sum of a first voltage and a second voltage; (c) means for performing a first cycle by multiplying a residue voltage of the integrator by 2; (d) means for performing a second cycle by integrating the second voltage in a first direction by means of the integrator if the comparator changes state or in a second direction opposite to the first direction if the comparator does not change state; and (e) means for performing a third cycle by integrating the input voltage in a direction that causes the output voltage of the integrator to equal either 2×
Vresidue−
Vref or 2×
Vresidue+Vref, wherein Vresidue is a residue voltage which is an output voltage of the integrator at the end of a preceding cycle and Vref is equal to the entire reference voltage value.
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Specification