METHOD AND CIRCUIT FOR PROGRAMMING A MEMORY CELL, IN PARTICULAR OF THE NOR FLASH TYPE

• US 20080259683A1
• Filed: 04/16/2008
• Published: 10/23/2008
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Numonyx BV (Micron Technology, Inc.)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Lisi, Carlo, Ghilardi, Tecla
• Granted Patent: US 7,656,712 B2
• Time in Patent Office: Days
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.

Claims

1. A programming method, comprising:

applying a continuous voltage to a drain terminal of a memory cell and a suitable programming voltage signal to a gate terminal of the memory cell;

applying a constant voltage to said gate terminal and regulating a voltage of said drain terminal while the constant voltage is applied to the gate terminal;

the regulating including maintaining the voltage of said drain terminal substantially at a fixed value until a threshold voltage value of said memory cell reaches a desired threshold voltage level; and

stopping the regulating in response to detecting that a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the threshold voltage of said memory cell reaching said desired threshold voltage level.

2. The programming method according to claim 1, wherein the fixed value of the drain voltage during said regulating is equal to the continuous voltage applied to the drain terminal.

3. The programming method according to claim 2, wherein said reference current value corresponds to the attainment of a threshold voltage level under a programming condition of said memory cell.

4. The programming method according to claim 1, further comprising a preliminary characterizing phase of said memory cell in which a programming current off-set is identified of said memory cell in correspondence with voltage values applied to said drain terminal thereof and corresponding to a programming drain voltage and to a reading drain voltage and in which a value of said reference current is established.

5. The programming method according to claim 4, wherein said preliminary characterizing phase establishes said value of said reference current equal to a minimum current value which allows a correct reading of said memory cell.

6. The programming method according to claim 4, wherein said preliminary characterizing phase establishes said value of said reference current equal to a minimum current value which allows a correct reading of said memory cell plus a suitable margin.

7. The programming method according to claim 4, wherein said preliminary characterizing phase is a statistical verify phase at a wafer level of a memory device that includes said memory cell.

8. The programming method according to claim 1, further comprising, after stopping the regulating, implementing a final program verify phase by applying, to the drain terminal of said memory cell, a reading drain voltage.

9. The programming method according to claim 8, wherein said regulating employs a feedback path suitable for maintaining a drain terminal of a regulation transistor coupled to said memory cell at a fixed potential, a source terminal of said regulation transistor being coupled to said drain terminal of said memory cell, in turn having a source terminal connected to a voltage reference.

10. The programming method according to claim 9, further comprising indirectly monitoring a drain current of said memory cell by comparing a gate voltage value at a gate terminal of said regulation transistor with a reference gate voltage value corresponding to a programming drain current of said memory cell, and ensuring at the same time that a voltage difference between drain and source terminals of said memory cell is maintained at said desired programming voltage value.

11. The programming method according to claim 10, wherein said indirectly monitoring employs a reference circuit coupled to said regulation transistor and including a further regulation transistor, similar in behavior to said regulation transistor and having a drain terminal connected to a programming drain voltage reference and a source terminal connected to a reference inner circuit node maintained at said desired programming drain voltage value.

12. The programming method according to claim 11, wherein said stopping includes disabling said regulation transistor by comparing said drain current of said memory cell with said reference current value, said drain current of said memory cell corresponding to its threshold voltage value, which is set at said desired reference drain voltage level, and maintaining its drain voltage level at a fixed value.

13. A programming circuit of a memory cell, comprising:

a selection circuit having a terminal for coupling to the memory cell;

a regulation transistor positioned between a first voltage reference and the selection circuit, said regulation transistor and said selection circuit being interconnected at a first inner circuit node;

a first voltage comparator having a first input terminal, a second input terminal feedback coupled to said first inner circuit node, and an output terminal coupled to a gate terminal of said regulation transistor;

a first reference circuit having an output terminal and structured to provide a first reference gate voltage value; and

a second voltage comparator having a first input terminal coupled to the reference circuit, a second input terminal feedback coupled to said output terminal of said first voltage comparator, and an output terminal coupled to an enable terminal of said first voltage comparator.

14. The programming circuit according to claim 13, wherein said reference circuit is structured to set said reference gate voltage value to correspond to a programming current value equal to a reference current limit value at which the voltage between drain and source terminals of said memory cell is maintained fixed at a value equal to a desired programming drain voltage value.

15. The programming circuit according to claim 14, wherein said reference circuit has a structure corresponding to a structure of said programming circuit and comprises a duplicated regulation transistor similar in behavior to said regulation transistor and having a drain terminal connected to said first voltage reference and a source terminal connected to a reference inner circuit node maintained at said desired programming drain voltage value.

16. The programming circuit according to claim 15, wherein said reference circuit further comprises:

a duplicated selection circuit positioned between said duplicated regulation transistor and a second voltage reference, said selection circuit showing a voltage—

current characteristic identical to that of said memory cell when programmed at a desired threshold voltage level, the duplicated selection circuit including a generator structured to generate said reference current limit value.

17. The programming circuit according to claim 16, wherein said generator is regulated so as to supply a reference current value determined during a verify phase at the wafer level of a memory device which comprises said memory cell to take into account the process variability of the manufacturing of said device.

18. The programming circuit according to claim 17, said reference circuit further comprises a third voltage comparator having a first input terminal, a second input terminal feedback connected to said reference inner circuit node, and an output terminal coupled to a gate terminal of said duplicated regulation transistor and structured to supply the gate terminal of said duplicated regulation transistor with said reference gate voltage value.

19. The programming circuit according to claim 13, further comprising an enable block coupled between said first voltage reference and said regulation transistor and including an enable transistor having a gate terminal coupled to the output terminal of the second voltage comparator.

20. The programming circuit according to claim 13, further comprising:

a second reference circuit having an output terminal coupled to said second voltage comparator and structured to provide a second reference gate voltage value; and

a selection pass-gate coupled between the output terminal of the second reference circuit and said second voltage comparator.

21. A memory device, comprising:

a memory cell; and

a programming circuit coupled to the memory cell and structured to program the memory cell, the programming circuit including;

a selection circuit having a terminal for coupling to the memory cell;

a regulation transistor positioned between a first voltage reference and the selection circuit, said regulation transistor and said selection circuit being interconnected at a first inner circuit node;

a first voltage comparator having a first input terminal, a second input terminal feedback coupled to said first inner circuit node, and an output terminal coupled to a gate terminal of said regulation transistor;

a first reference circuit having an output terminal and structured to provide a first reference gate voltage value; and

a second voltage comparator having a first input terminal coupled to the reference circuit, a second input terminal feedback coupled to said output terminal of said first voltage comparator, and an output terminal coupled to an enable terminal of said first voltage comparator.

22. The memory device according to claim 21, wherein said reference circuit is structured to set said reference gate voltage value to correspond to a programming current value equal to a reference current limit value at which the voltage between drain and source terminals of said memory cell is maintained fixed at a value equal to a desired programming drain voltage value.

23. The memory device according to claim 22, wherein said reference circuit has a structure corresponding to a structure of said programming circuit and comprises a duplicated regulation transistor similar in behavior to said regulation transistor and having a drain terminal connected to said first voltage reference and a source terminal connected to a reference inner circuit node maintained at said desired programming drain voltage value.

24. The memory device according to claim 23, wherein said reference circuit further comprises:

a duplicated selection circuit positioned between said duplicated regulation transistor and a second voltage reference, said selection circuit showing a voltage—

current characteristic identical to that of said memory cell when programmed at a desired threshold voltage level, the duplicated selection circuit including a generator structured to generate said reference current limit value.

25. The memory device according to claim 24, wherein said generator is regulated so as to supply a reference current value determined during a verify phase at the wafer level of a memory device which comprises said memory cell to take into account the process variability of the manufacturing of said device.

26. The memory device according to claim 25, said reference circuit further comprises a third voltage comparator having a first input terminal, a second input terminal feedback connected to said reference inner circuit node, and an output terminal coupled to a gate terminal of said duplicated regulation transistor and structured to supply the gate terminal of said duplicated regulation transistor with said reference gate voltage value.

27. The memory device according to claim 21, wherein the programming circuit includes an enable block coupled between said first voltage reference and said regulation transistor and including an enable transistor having a gate terminal coupled to the output terminal of the second voltage comparator.

28. The memory device according to claim 21, wherein the programming circuit includes:

a second reference circuit having an output terminal coupled to said second voltage comparator and structured to provide a second reference gate voltage value; and

a selection pass-gate coupled between the output terminal of the second reference circuit and said second voltage comparator.