STATE-MONITORING MEMORY ELEMENT
First Claim
1. A system, comprising:
- at least one state-monitoring memory element having a reduced ability to retain a logic state compared to a normal memory element; and
a logic analyzer to detect a failure in the state-monitoring memory element and to generate an indicator of failure responsive to the detection.
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Accused Products
Abstract
Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC'"'"'s state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage.
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Citations
20 Claims
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1. A system, comprising:
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at least one state-monitoring memory element having a reduced ability to retain a logic state compared to a normal memory element; and a logic analyzer to detect a failure in the state-monitoring memory element and to generate an indicator of failure responsive to the detection. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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configuring the state-monitoring memory element to have a reduced ability to retain a logic state compare to a normal memory element; detecting a failure in the state-monitoring memory element; and generating an indicator of failure responsive to detecting the failure in the state-monitoring memory element. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A system, comprising:
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means for configuring a state-monitoring memory element to have a reduced ability to retain a logic state compared to a normal memory element, such that the state-monitoring memory element is more likely to fail than the normal memory element when an input voltage associated with the state-monitoring memory element drops below a predetermined threshold voltage; means for detecting a failure in the state-monitoring memory element; and means for generating an indicator of failure responsive to detecting a failure in the state-monitoring memory element. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification