Tv-Pc Architecture
First Claim
1. An apparatus including at least a first hardware part (AP1) and a second hardware part (AP2), where each of the first and second part include a respective processing element (CPU-1, CPU-2) and a respective signal connection to a respective memory element (MEM-1, MEM-2) for providing program code to the processing element of the respective part;
- the apparatus further includes a third hardware part (AP3) including at least one peripheral element acting as a source and/or destination of data; and
a fourth hardware part including an I/O network (AP-4) for enabling communication between elements of the first and third part under control of first configuration data and for enabling communication between elements of the second and third part under control of distinct second configuration data.
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Accused Products
Abstract
An apparatus includes at least a first hardware part (AP1) and a second hardware part (AP2). Each of the first and second part include a respective processing element (CPU-1, CPU-2) and a respective signal connection to a respective memory element (MEM-1, MEM-2) for providing program code to the processing element of the respective part. The apparatus further includes a third hardware part (AP3) including at least one peripheral element acting as a source and/or destination of data. A fourth hardware part of the apparatus includes an I/O network (AP-4) for enabling communication between elements of the first and third part under control of first configuration data and for enabling communication between elements of the second and third part under control of distinct second configuration data.
12 Citations
16 Claims
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1. An apparatus including at least a first hardware part (AP1) and a second hardware part (AP2), where each of the first and second part include a respective processing element (CPU-1, CPU-2) and a respective signal connection to a respective memory element (MEM-1, MEM-2) for providing program code to the processing element of the respective part;
the apparatus further includes a third hardware part (AP3) including at least one peripheral element acting as a source and/or destination of data; and
a fourth hardware part including an I/O network (AP-4) for enabling communication between elements of the first and third part under control of first configuration data and for enabling communication between elements of the second and third part under control of distinct second configuration data.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A processing assembly including a first hardware part (AP-1) including a first processing element (CPU-1) and signal connection to a first memory element (MEM-1) for providing program code to the first processing element;
- a third hardware part (AP3) including at least one peripheral element acting as a source and/or destination of data; and
a fourth hardware part including an I/O network (AP-4) coupled to the first an third part for enabling communication between elements of the first and third part under control of first configuration data;
the fourth hardware part further including a signal connection for connection to a second hardware part (AP2) including a second processing element (CPU-2) and a signal connection to a second memory element (MEM-2) for providing program code to the second processing element;
the fourth part being operable to receive distinct second configuration data via the signal connection to enable communication between elements of the second and third part under control of the second configuration data.
- a third hardware part (AP3) including at least one peripheral element acting as a source and/or destination of data; and
Specification