DISPLAY INTERFACE BUFFER

• US 20080263260A1
• Filed: 12/27/2007
• Published: 10/23/2008
• Est. Priority Date: 04/18/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Wright, David A., Erickson, Jeffrey Stephen, Foreman, John B.
• Granted Patent: US 8,564,605 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters

Abstract

A display interface buffer includes a general purpose memory to store data capable of being displayed on a panel, a plurality of display drivers to receive data from the general purpose memory, each of the display drivers to drive a different portion of the panel with the data, and processor or a direct memory access controller to access data in the general purpose memory and to provide the data to the display drivers for presentation on the panel.

Claims

1. A device comprising:

a general purpose memory to store data capable of being displayed on a panel;

a plurality of display drivers to receive data from the general purpose memory, each of the display drivers to drive a different portion of the panel with the data; and

a direct memory access controller to access data in the general purpose memory and to provide the data to the display drivers for presentation on the panel.

2. The device of claim 1 where at least one of the display drivers includes

a First-In-First-Out (FIFO) buffer to store the data received from the direct memory access controller;

and

a drive voltage selector to select at least one of a plurality of reference voltages responsive to the data stored by the FIFO buffer, the selected reference voltage to drive the panel according to at least part of the data stored by the FIFO buffer.

3. The device of claim 2 where the FIFO buffer includes

a first memory element to receive data from the direct memory access controller;

and

a second memory element to receive data from the first memory element and to provide data to the drive voltage selector.

4. The device of claim 3 where the first memory element and the second memory element are flip-flop buffers.

5. The device of claim 3 including an address decoder to decode an address from the direct memory access controller, the address to indicate which display driver corresponds to the display pin, where the second memory element receives the display data stored by the first memory element responsive to the decoded address.

6. The device of claim 2 where at least one of the display drivers includes a general purpose interface controller to receive data from the FIFO buffer and provide the data to an input-output pin as general purpose I/O data during a general purpose data mode, where the input-output pin the provide the data to the display drivers for presentation on the panel.

7. The device of claim 1 including transaction descriptors reflecting a display memory map that direct the direct memory access controller to access display data in the general purpose memory, the transaction descriptors to indicate which of the plurality of display drivers is to receive each bit of the accessed display data for presentation on the panel.

8. The device of claim 7 where the direct memory access controller retrieves display data from the general purpose memory responsive to at least one of the transaction descriptors, and provides at least one of the display drivers the display data and an address that uniquely identifies the display driver to receive the display data.

9. A method comprising:

accessing data in the general purpose memory according to one or more transaction descriptors;

identifying one or more display drivers to present the accessed data on a panel by driving a column or segment of the panel; and

providing the accessed data to the identified display drivers according to the transcription descriptors.

10. The method of claim 9 where at least one of the display drivers includes

a First-In-First-Out (FIFO) buffer to store the data provided according to the transaction descriptors;

and

a drive voltage selector to select at least one a plurality of reference voltages responsive to the data stored by the FIFO buffer, the selected reference voltage to drive the panel according to the data stored by the FIFO buffer.

11. The method of claim 10 where the FIFO buffer includes

a first memory element to receive data from the direct memory access controller;

and

a second memory element to receive the display data from the first memory element and to provide the display data to the drive voltage selector.

12. The method of claim 10 includes

receiving general purpose I/O data during a general purpose data mode;

and

providing the general purpose I/O data to an input-output pin via the display drivers, where the display drivers input-output pin.

13. The method of claim 12 includes

enabling a general purpose interface controller in the display drivers to provide general purpose I/O data to the input-output pin during the general purpose data mode;

and

disabling a buffer in the display drivers from providing data to the panel via the input-output pin during the general purpose data mode.

14. The method of claim 12 includes

enabling a buffer in the display drivers to provide data to the panel via the input-output pin during a display driving mode;

and

disabling a general purpose interface controller in the display drivers from providing general purpose I/O data to the input-output pin during the display driving mode.

15. A device comprising:

structure for accessing data in the general purpose memory according to one or more transaction descriptors;

structure for identifying one or more display drivers to present the accessed data on a panel by driving a column or segment of the panel; and

structure for providing the accessed data to the identified display drivers according to the transaction descriptors.

16. The device of claim 15 where at least one of the display drivers includes

a First-In-First-Out (FIFO) buffer to store the data received from the direct memory access controller;

and

a drive voltage selector to select at least one a plurality of bias voltages responsive to the data stored by the FIFO buffer, the selected bias voltage to drive the panel according to the data stored by the FIFO buffer.

17. The device of claim 16 where the FIFO buffer includes

a first memory element to receive data from the direct memory access controller;

and

a second memory element to receive the display data from the first memory element and to provide the display data to the drive voltage selector.

18. The device of claim 16 includes

structure for receiving general purpose I/O data during a general purpose data mode;

and

structure for providing the general purpose I/O data to an input-output pin via the display drivers, where the display drivers input-output pin.

19. The device of claim 18 includes

structure for enabling a general purpose interface controller in the display drivers to provide general purpose I/O data to the input-output pin during the general purpose data mode;

and

structure for disabling a buffer in the display drivers from providing data to the panel via the input-output pin during the general purpose data mode.

20. The device of claim 18 includes

structure for enabling a buffer in the display drivers to provide data to the panel via the input-output pin during a display driving mode;

and

structure for disabling a general purpose interface controller in the display drivers from providing general purpose I/O data to the input-output pin during the display driving mode.