Electrical Diagnostic Circuit and Method for the Testing and/or the Diagnostic Analysis of an Integrated Circuit
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Abstract
An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input.
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Citations
80 Claims
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1-40. -40. (canceled)
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41. An electrical diagnostic circuit for the testing and/or the diagnostic analysis of an integrated circuit comprising:
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a plurality of external inputs (En) for receiving digital values; a plurality of essentially similar, series-connected switching units comprising; each switching unit is connected to one external input for receiving a test signal of an integrated circuit; each switching unit has an internal input for an input signal from a switching unit arranged upstream or downstream, the switching units are configured to be controllable such that an input signal present at the internal input of a switching unit, in dependence on a control signal of the switching unit, are forwarded either unchanged to the internal input of the switching unit arranged downstream or to the circuit output and/or are fed back to an internal input of a switching unit arranged upstream, or are combined with the test signal in each case present at the external input and the combination value determined from this combination is forwarded to the internal input of the switching unit in each case arranged downstream or to the circuit output and/or is fed back to the internal input of a switching unit arranged upstream; and a circuit output for outputting an output value. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 57, 58, 59, 60, 61, 64, 65)
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52. An electrical diagnostic circuit for the testing and/or the diagnostic analysis of an integrated circuit comprising:
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a plurality of external inputs (En) for receiving digital values; a plurality of essentially similar, series-connected switching units comprising; each switching unit is connected to one external input for receiving a test signal of an integrated circuit; each switching unit has an internal input for an input signal from a switching unit arranged upstream or downstream, the switching units are configured to be controllable such that an input signal present at the internal input of a switching unit, in dependence on a control signal of the switching unit, are forwarded either unchanged to the internal input of the switching unit arranged downstream or to the circuit output and/or are fed back to an internal input of a switching unit arranged upstream, or are combined with the test signal in each case present at the external input and the combination value determined from this combination is forwarded to the internal input of the switching unit in each case arranged downstream or to the circuit output and/or is fed back to the internal input of a switching unit arranged upstream; and a circuit output for outputting an output value comprising wherein the first switching unit has an AND gate and a storage unit and in that all further switching units have one gate each, particularly an exclusive OR gate (XOR2-XORn), one multiplexer each and one storage unit each. - View Dependent Claims (53, 54, 55, 56)
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62. A method for testing and/or for the diagnostic analysis of an integrated circuit, comprising:
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providing an electrical diagnostic circuit which has n external inputs for receiving test data of n parallel datastreams of an integrated circuit to be tested and/or to be diagnosed and which is capable of generating signatures from the received test data, the test data present at the n external inputs selectively being included or not included in the generation of the signatures, connecting the electrical diagnostic circuit to the integrated circuit to be tested and/or to be diagnosed, in such a manner that the n inputs of the electrical diagnostic circuit are present at the n outputs of the integrated circuit; controlling the switching units of the electrical diagnostic circuit in such a manner that the test data in each case present at the external inputs are included in the generation of the signatures; detecting and processing the test data of the integrated circuit to be tested and/or to be diagnosed to form at least one signature in one or in more successive test runs through the electrical diagnostic circuit; checking the signature for correctness by means of the test by comparing the signatures determined in the test with the correct signature stored in the tester or determined by the tester; if at least one errored signature has been determined, carrying out the following processes; performing k successive test runs, wherein in each case only those data, present at the input Ei, of the n datastreams in the jth run are included in the compacting in the electrical diagnostic circuit if the binary coefficient ai,j of the equations for determining the control points of a linear separable error-correcting code with n information points u1, . . . , un and with k control points v1, . . . , vk is equal to one, the k control points v1, . . . , vk being determined by the k binary equations from the n information points. Determining the errored elements in the n datastreams, particularly the errored scan cells of the diagnosed integrated circuit from the deviations of the observed output signatures output by the electrical diagnostic circuit at its output in the k test runs
[y1b,y2b,y3b, . . . ]from the corresponding correct output signatures
[y1k,y2k,y3k, . . . ]- View Dependent Claims (63, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75)
wherein the coefficients ai,j with 1≦
i≦
k, 1≦
j≦
n assume the values zero or one, the switching units of the electrical diagnostic circuit being controlled in such a manner that the test data present at the jth external input in the ith run are only subjected to a combination in the switching units if the control signal ci,j, with 1≦
i≦
k, 1≦
j≦
n, assumes the value one, whereby the control signal ci,j assumes the value zero if the associated coefficient ai,j assumes the value zero or if an indeterminate value in the datastream is to be blanked out.
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71. The method of claim 62, comprising wherein the value of the control signal present at the first input of the AND gate assumes the value zero if an indeterminate value is present at the output of the upstream storage element Dn, and thus at its second input.
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72. The method of claim 62, comprising wherein performing successive test runs is carried out as follows:
- carrying out k successive test runs by the switching units of the electrical diagnostic circuit being controlled in accordance with the binary coefficients ai,j of the equations for determining the control points v1, . . . , vk of a linear separable error-correcting code with n information points u1, . . . , un and with k control points v1, . . . , vk, in such a manner that the test data (u, t, s, r) present at the jth external input (Ej) in the ith run are only subjected to a combination in the switching units of the electrical diagnostic circuit when the binary control signal ci,j, with 1≦
i≦
k, 1≦
j≦
n, assumes the value one, whereby the control signal ci,j assumes the value zero when the associated coefficient ai,j in the linear equations for determining the k control points of the error-detecting code assumes the value zero or when an indeterminate value in the datastream is to be blanked out, the k control points v1, . . . , vk being determined from the k binary equationsfrom the n information points.
- carrying out k successive test runs by the switching units of the electrical diagnostic circuit being controlled in accordance with the binary coefficients ai,j of the equations for determining the control points v1, . . . , vk of a linear separable error-correcting code with n information points u1, . . . , un and with k control points v1, . . . , vk, in such a manner that the test data (u, t, s, r) present at the jth external input (Ej) in the ith run are only subjected to a combination in the switching units of the electrical diagnostic circuit when the binary control signal ci,j, with 1≦
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73. The method of claim 72, comprising wherein the multiplexers of the switching units are controlled by the control signals.
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74. The method of claim 72, comprising wherein a selection circuit which controls the input into the electrical diagnostic circuit is provided between the outputs (An) of the integrated circuit and the inputs (En) of the electrical diagnostic circuit.
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75. Using the method of claim 72 for testing and/or for the diagnostic analysis of printed board assemblies or of circuit boards.
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76. A computer program for carrying out a method for testing an integrated circuit comprising:
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providing an electrical diagnostic circuit which has n external inputs for receiving test data of n parallel datastreams of an integrated circuit to be tested and/or to be diagnosed and which is capable of generating signatures from the received test data, the test data present at the n external inputs selectively being included or not included in the generation of the signatures, connecting the electrical diagnostic circuit to the integrated circuit to be tested and/or to be diagnosed, in such a manner that the n inputs of the electrical diagnostic circuit are present at the n outputs of the integrated circuit; controlling the switching units of the electrical diagnostic circuit in such a manner that the test data in each case present at the external inputs are included in the generation of the signatures; detecting and processing the test data of the integrated circuit to be tested and/or to be diagnosed to form at least one signature in one or in more successive test runs through the electrical diagnostic circuit; checking the signature for correctness by means of the test by comparing the signatures determined in the test with the correct signature stored in the tester or determined by the tester; if at least one errored signature has been determined, carrying out the following processes; performing k successive test runs, wherein in each case only those data, present at the input Ei, of the n datastreams in the jth run are included in the compacting in the electrical diagnostic circuit if the binary coefficient ai,j of the equations for determining the control points of a linear separable error-correcting code with n information points u1, . . . , un and with k control points v1, . . . , vk is equal to one, the k control points v1, . . . , vk being determined by the k binary equations from the n information points. Determining the errored elements in the n datastreams, particularly the errored scan cells of the diagnosed integrated circuit from the deviations of the observed output signatures output by the electrical diagnostic circuit at its output in the k test runs
[y1b,y2b,y3b, . . . ]from the corresponding correct output signatures
[y1k,y2k,y3k, . . . ].- View Dependent Claims (77, 78, 79, 80)
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Specification