Microfabricated miniature grids

• US 20080265173A1
• Filed: 04/11/2008
• Published: 10/30/2008
• Est. Priority Date: 05/07/2004
• Status: Active Grant

• Current Assignee: Stillwater Scientific Instruments, Inc., The University Of Maine
• Original Assignee: Stillwater Scientific Instruments, Inc., The University Of Maine
• Inventors: Collins, Scott, LeGore, Lawrence J., Smith, Rosemary, Frederick, Brian G.
• Granted Patent: US 7,829,864 B2
• Time in Patent Office: Days
• US Class Current: 250/396R
• CPC Class Codes: H01J 49/0018 Microminiaturised spectrometers, e.g. chip-integrated devices, Micro-Electro-Mechanical Systems [MEMS]
• CPC Class Codes: H01J 49/061 Ion deflecting means, e.g. ion gates
• CPC Class Codes: H01J 9/14 of non-emitting electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A grid structure and method for manufacturing the same. The grid is used for gating a stream of charged particles in certain types of particle measurement instruments, such as ion mobility spectrometers and the like. The methods include various microfabrication techniques for etching and/or depositing grid structure materials on a silicon substrate.

Claims

1. An integrated microfabricated grid for controlling a charged particle stream, the grid formed of a plurality of electrically isolated conductive elements, comprising:

a substrate to serve as a support for said conductive elements at one of an end thereof, or at another support location within the grid;

a hole in the substrate to allow the charged particle stream to pass therethrough; and

the conductive elements lying in a common plane with one another, and formed from a microfabricated, integral layer disposed adjacent the substrate, the conductive elements having at least one dimension of 10 micrometers (um) or less.

2. A grid as in claim 1 wherein the grid further comprises:

a first and second set of electrically isolated, equally spaced conductors that lie in the same plane both sets of conductors also microfabricated on an integral layer insulated from the substrate, the respective sets of conductors to be applied to alternate electrical potentials.

3. A grid as in claim 1, wherein said conductive elements are single crystal.

4. A grid as in claim 1, wherein said conductive elements are a heavily doped semiconductor.

5. A grid as in claim 1 wherein the semiconductor is selected from a group consisting of silicon, germanium, or a compound semiconductor such as GaAs.

6. A grid as in claim 1, where the microfabricated elements are formed with Deep Reactive Ion Etching (DRIE).

7. A grid as in claim 1, where the microfabricated conductive elements layer are formed using photolithography.

8. A grid as in claim 1, wherein the conductive elements and substrate are microfabricated from a silicon on insulator (SOI) wafer, the SOI wafer having a silicon layer formed adjacent to a silicon oxide insulating layer.

9. A grid as in claim 1, wherein the conductive elements are microfabricated using an additive process such as LIGA.

10. A grid as in any of claim 1 wherein the conductive elements are further comprised of a first and second set of electrically isolated, equally spaced conductors, and the respective set of conductors are applied to alternate potentials by a common bus bar also formed as integrated part on the substrate.

11. A grid as in claim 8 wherein the substrate that provides support for the conductive elements is an oxide coated micromachined silicon wafer.

12. A grid as in claim 1 wherein the conductive elements are supported at the both ends thereof.

13. A grid as in claim 1 wherein the conductive elements are supported at a mid portion.