Device structure and manufacturing method using HDP deposited source-body implant block

• US 20080265289A1
• Filed: 04/30/2007
• Published: 10/30/2008
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik K., Tai, Sung-Shan, Bhalla, Anup, Hebert, Francios
• Granted Patent: US 8,035,159 B2
• Time in Patent Office: Days
• US Class Current: 257/263
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Claims

1. A trenched semiconductor power device comprising a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near said top surface above a drain region disposed on a bottom surface of a substrate, wherein said semiconductor power device further comprising:

an implanting-ion block disposed above said top surface on a mesa area next to said body region having a thickness substantially for blocking body implanting ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced.

2. The trenched power semiconductor power device of claim 1 wherein:

said implanting-ion block further comprising an oxide layer having a thickness larger than 0.3 micron.

3. The trenched power semiconductor power device of claim 1 wherein:

said implanting-ion block further comprising a chemical vapor deposited (CVD) oxide layer

4. The trenched power semiconductor power device of claim 1 wherein:

said implanting-ion block further comprising a thermal oxide layer

5. The trenched power semiconductor power device of claim 1 wherein:

said implanting-ion block further comprising a high-density plasma (HDP) oxide layer

6. The trenched power semiconductor power device of claim 1 further comprising:

a high-density plasma (HDP) deposited thick oxide layer disposed on a bottom surface of said trenched gate having a thickness greater than a gate oxide layer padding sidewalls of said trenched gate; and

said implanting-ion block further comprising a high-density plasma (HDP) oxide layer having a thickness larger than 0.3 micron formed simultaneously with said HDP deposited thick oxide layer disposed on said bottom surface of said trenched gate.

7. The trenched power semiconductor power device of claim 1 wherein:

said body region is separated as two separated body regions disposed on two opposite sides of said trenched gate.

8. The trenched power semiconductor power device of claim 1 wherein:

said body region constituting a merged body region merged from two separated body regions disposed on two opposite sides of said trenched gate having a inverted V pinnacle point near a bottom center of said body region.

9. The trenched power semiconductor power device of claim 1 further comprising:

an insulation protective layer disposed on top of said semiconductor power device having a plurality of contact openings opened therethrough and extending to said body region and said semiconductor power device further including a source/body ohmic contact dopant region disposed beneath each of said contact openings for enhancing ohmic contact to said body/source region.

10. The trenched power semiconductor power device of claim 1 wherein:

said body region constituting a merged body region merged from two separated body regions disposed on two opposite sides of said trenched gate having a inverted V pinnacle point near a bottom center of said body region wherein said semiconductor power device having a configuration for providing a lowest breakdown voltage near said inverted V pinnacle point for inducing a breakdown near a bottom of said body region.

11. The trenched power semiconductor power device of claim 1 wherein:

said semiconductor power device further comprising a metal oxide semiconductor field effect transistor (MOSFET) device.

12. The trenched power semiconductor power device of claim 1 wherein:

said semiconductor power device further comprising a N-channel metal oxide semiconductor field effect transistor (MOSFET) device.

13. The trenched power semiconductor power device of claim 1 wherein:

said semiconductor power device further comprising a P-channel metal oxide semiconductor field effect transistor (MOSFET) device.

14. The trenched power semiconductor power device of claim 1 further comprising:

a termination area wherein said implanting-ion block having a greater width than said implanting-ion block on said mesa area for separating said body regions and forming floating body regions in said termination area to form at least a guard ring in a trenched gate surrounded by said floating body region in said termination area.

15. The trenched power semiconductor power device of claim 1 further comprising:

an integrated Schottky field effect transistor (FET) including a body dopant region, with a higher dopant concentration than said body region, disposed adjacent to said source region, and said body dopant region having a region boundary substantially aligned with said ion-implanting block.

16. The trenched power semiconductor power device of claim 1 wherein:

said trenched gate further comprising a split gate including a lower gate segment covered by an insulation layer and an upper gate segment above said insulation layer.

17. The trenched power semiconductor power device of claim 1 wherein:

said trenched gate further comprising a split gate including a lower gate segment covered by an insulation layer and an upper gate segment above said insulation layer.; and

said trenched gate further including a thick oxide layer disposed on a bottom surface of said trenched gate having a thickness greater than a gate oxide layer padding sidewalls of said trenched gate.

18. The trenched power semiconductor power device of claim 17 wherein:

a thick oxide layer disposed on said bottom of said trenched gate is a high-density plasma (HDP) deposited thick oxide layer and said implanting-ion block further comprising a HDP deposited oxide layer formed simultaneously with said thick oxide layer disposed on said bottom of said trenched gate.

19. A trenched power semiconductor power device comprising:

a high-density plasma (HDP) deposited thick oxide layer disposed on a bottom surface of a trenched gate having a thickness greater than a gate oxide layer padding sidewalls of said trenched gate; and

implanting-ion blocks comprising HDP oxide layer having a thickness larger than 0.3 micron formed simultaneously with said HDP deposited thick oxide layer disposed on said bottom surface of said trenched gate.

20. A method for manufacturing a trenched semiconductor power device comprising:

opening a plurality of trenches from a top surface of a semiconductor substrate and forming a gate insulation layer on sidewalls and bottom surface of said trenches; and

forming an implanting-ion block above said top surface in a mesa area at a distance away from said trenches for blocking body implanting ions and source ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced.

21. The method of claim 20 wherein:

said step of forming said implanting-ion block further comprising a step of forming an oxide layer in said mesa area having a thickness larger than 0.3 micron.

22. The method of claim 20 wherein:

said step of forming said implanting-ion block further comprising a step of applying a chemical vapor deposition (CVD) to form an oxide layer

23. The method of claim 20 wherein:

said step of forming said implanting-ion block further comprising a step of applying a thermal oxidation to form an oxide layer

24. The method of claim 20 wherein:

said step of forming said implanting-ion block further comprising a step of applying a high-density plasma (HDP) deposition process to deposit an oxide layer in said mesa area

25. The method of claim 20 further comprising:

applying a high-density plasma (HDP) deposition process for depositing a thick oxide layer on a bottom surface of said trenched gate having a thickness greater than a gate oxide layer padding sidewalls of said trenched gate; and

forming said implanting-ion block simultaneously, by using said HDP deposition process for depositing a thick oxide layer on said bottom surface of said trench, to form a HDP oxide layer as said implanting-ion block in said mesa area having a thickness larger than 0.3 micron

26. The method of claim 20 further comprising:

implanting body ions into said semiconductor substrate with said implanting-ion block blocking said mesa area and diffusing said body ions into a body region with said body region separated as two separated body regions disposed on two opposite sides of said trenches.

27. The method of claim 20 further comprising:

implanting body ions into said semiconductor substrate with said implanting-ion block blocking said mesa area and diffusing said body ions into a merged body region with said body region merged from two separated body regions disposed on two opposite sides of said trenched gate having a inverted V pinnacle point near a bottom center of said body region.

28. The method of claim 20 further comprising:

forming an insulation protective layer on top of said semiconductor power device and opening a plurality of contact openings therethrough and extending to a body region; and

implanting a source-body ohmic contact dopant to form a source/body ohmic contact dopant region beneath each of said contact openings for enhancing ohmic contact to said body/source region.

29. The method of claim 20 further comprising:

implanting body ions into said semiconductor substrate with said implanting-ion block blocking said mesa area and diffusing said body ions into a merged body region with said body region merged from two separated body regions disposed on two opposite sides of said trenched gate having a inverted V pinnacle point near a bottom center of said body region; and

configuring said semiconductor power device to have a lowest breakdown voltage near said inverted V pinnacle point for inducing a breakdown near a bottom of said body region.

30. The method of claim 20 further comprising:

manufacturing said semiconductor power device as a metal oxide semiconductor field effect transistor (MOSFET) device.

31. The method of claim 20 further comprising:

manufacturing said semiconductor power device as a N-channel metal oxide semiconductor field effect transistor (MOSFET) device.

32. The method of claim 20 further comprising:

manufacturing said semiconductor power device as a P-channel metal oxide semiconductor field effect transistor (MOSFET) device.

33. The method of claim 20 further comprising:

forming said implanting-ion blocks in a termination area with a greater width than said implanting-ion block on said mesa area for separating body ion implanting regions to form floating body regions in said termination area thus form at least a guard ring in a trench surrounded by said floating body region in said termination area.

34. The method of claim 20 further comprising:

implanting and diffusing body and source ions with said implanting ion blocks in said mesa area to form body and source regions surrounding said trenches; and

etching off a portion of said implanting ion blocks for implanting body dopant ions with a higher dopant concentration than said body region to form high-concentration body dopant regions between said source regions and said body regions to form an integrated Schottky field effect transistor (FET).

35. The method of claim 20 further comprising:

forming trenched gate in each of said trenches as a split gate including a lower gate segment covered by an insulation layer and an upper gate segment above said insulation layer.

36. The method of claim 20 further comprising:

applying a HDP deposition process to form a thick oxide layer on bottom surface of said trenches simultaneously with and implanting ion blocks as HDP oxide layer and forming split gate in each of said trenches.