MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS

• US 20080265291A1
• Filed: 04/30/2007
• Published: 10/30/2008
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zhu, Ronghua, Bose, Amitava, Khemka, Vishnu K., Roggenbauer, Todd C.
• Granted Patent: US 7,851,889 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well. An area (510) comprising regions of alternating conductivities is then formed in the semiconductor well.

Claims

1. A semiconductor device, comprising:

a semiconductor body comprising a surface;

a transistor source located in the semiconductor body proximate the surface; and

a first area comprising alternating p-type regions and n-type regions located in the transistor source.

2. The semiconductor device of claim 1, the source further comprising a silicide layer covering at least a portion of the first area.

3. The semiconductor device of claim 1, further comprising a second area comprising alternating p-type regions and n-type regions located in the transistor source.

4. The semiconductor device of claim 3, the source further comprising one of a p-type region and an n-type region separating the first area and the second area.

5. The semiconductor of claim 4, further comprising a first polysilicon region adjacent the first area.

6. The semiconductor of claim 5, further comprising a second polysilicon region adjacent the second area.

7. The semiconductor device of claim 1, wherein the first area comprises a silicided block region separating a p-type region from an n-type region.

8. The semiconductor device of claim 1, further comprising:

a first polysilicon region located in the transistor source; and

a second polysilicon region located in the transistor source, the first area separating the first and second polysilicon regions.

9. A semiconductor device, comprising:

a semiconductor body comprising a surface and a first conductivity type;

a transistor source located in the semiconductor body proximate the surface; and

a first plurality of regions comprising a second conductivity type located in the transistor source, the first plurality of regions and the semiconductor body forming a first area of alternating regions of the first and second conductivity types.

10. The semiconductor device of claim 9, further comprising a second plurality of regions comprising the second conductivity type located in the semiconductor body, the second plurality of regions and the semiconductor body forming a second area of alternating regions of the first and second conductivity types.

11. The semiconductor device of claim 10, further comprising a doped region comprising one of the first conductivity type and the second conductivity type separating the first and second areas.

12. The semiconductor device of claim 9, wherein the first conductivity type is an n-type conductivity and the second conductivity type is a p-type conductivity.

13. The semiconductor device of claim 9, wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity.

14. A method for fabricating a semiconductor device comprising a substrate, the method comprising:

implanting a semiconductor well comprising a first conductivity in the substrate;

implanting a first plurality of doped regions comprising a second conductivity in the semiconductor well; and

forming a first area comprising alternating conductivity regions of the first conductivity and the second conductivity in the semiconductor well, wherein the first area comprises alternating regions of the first plurality of doped regions and regions of the semiconductor well.

15. The method of claim 14, further comprising:

forming a second area comprising alternating conductivity regions of the first conductivity and the second conductivity in the semiconductor well, wherein the second area comprises alternating regions of the first plurality of doped regions and regions of the semiconductor well; and

implanting a conductivity region in the semiconductor well between the first and second areas.

16. The method of claim 14, further comprising forming a silicide layer over at least a portion of the first area.

17. The method of claim 14, further comprising implanting a second plurality of doped regions comprising the first conductivity in the second semiconductor well, wherein the first area comprises alternating conductivity regions of the first plurality and the second plurality of doped regions.

18. The method of claim 17, further comprising:

forming a second area comprising alternating conductivity regions of the first conductivity and the second conductivity in the semiconductor well, wherein the second area comprises alternating regions of the first plurality and the second plurality of doped regions; and

implanting a conductivity region in the semiconductor well between the first and second areas.

19. The method of claim 17, further comprising forming at least one silicided block region in the first area between a first region of the first plurality of doped regions and a second region of the second plurality of doped regions.

20. The method of claim 17, further comprising forming a silicide layer over at least a portion of the first area.