INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES

• US 20080265305A1
• Filed: 06/25/2008
• Published: 10/30/2008
• Est. Priority Date: 04/24/2007
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Len Mei, Yue-Song He
• Inventors: Mei, Len, He, Yue-Song
• Granted Patent: US 7,808,032 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A floating gate memory cell'"'"'s channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate'"'"'s top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate'"'"'s bottom surface may also comes down to a level below the top of the protrusion. The floating gate'"'"'s bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion'"'"'s height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion'"'"'s height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

Claims

1. An integrated circuit comprising a nonvolatile memory cell comprising:

a semiconductor substrate having an upward protrusion;

a first dielectric feature present at least on the protrusion'"'"'s sidewalls on at least two sides of the protrusion; and

a floating gate present at least over said sidewalls on at least said two sides of the protrusion and separated from the protrusion by the first dielectric feature, the floating gate having a top surface coming down along the at least two sides of the protrusion to a level below a top of the protrusion.

2. The integrated circuit of claim 1 wherein the nonvolatile memory cell further comprises:

a second dielectric feature over the floating gate; and

a conductive gate over the second dielectric feature, the conductive gate having a bottom surface coming down along at least the two sides of the protrusion to a level below the top of the protrusion.

3. The integrated circuit of claim 1 wherein:

the memory cell is one of a first plurality of nonvolatile memory cells in the integrated circuit;

the first dielectric feature is one of a plurality of first dielectric features which belong to the memory cells, each first dielectric feature being present at least on said sidewalls on at least said two sides of the protrusion;

the floating gate is one of a plurality of floating gates which belong to the memory cells, each floating gate being present at least over said sidewalls on at least said two sides of the protrusion, each floating gate being separated from the semiconductor substrate by the respective first dielectric feature, each floating gate having a top surface coming down along the at least two sides of the protrusion to a level below the top of the protrusion, each two adjacent cells having a shared source/drain region at least partially located in the protrusion.

4. The integrated circuit of claim 3 wherein:

the protrusion is one of a plurality of protrusions of the semiconductor substrate;

the first plurality of nonvolatile memory cells is one of a plurality of first pluralities of nonvolatile memory cells in the integrated circuit, each first plurality of the memory cells being associated with a respective one of said protrusions, different protrusions being associated with respective different first pluralities of the memory cells;

wherein in each first plurality of the memory cells, each memory cell comprises;

a first dielectric feature on the associated protrusion'"'"'s sidewalls on at least two sides of the associated protrusion; and

a floating gate present at least over said sidewalls of the associated protrusion over at least the two sides of the associated protrusion, the floating gate being separated from the associated protrusion by the respective first dielectric feature, the floating gate having a top surface coming down along the at least two sides of the associated protrusion to a level below a top of the associated protrusion.

5. The integrated circuit of claim 4 further comprising a substrate isolation region between two of the protrusions, the substrate isolation region being a dielectric region whose bottom surface is lower than a bottom of the two adjacent protrusions.

6. The integrated circuit of claim 4 further comprising a plurality of conductive lines each of which provides a conductive gate to each of a plurality of the memory cells associated with different protrusions.

7. The integrated circuit of claim 6 wherein each said conductive gate is present on at least the two sides of the associated protrusion over the respective floating gate.

8. An integrated circuit comprising a nonvolatile memory cell comprising:

a semiconductor substrate having an upward protrusion;

a first dielectric feature present at least on the protrusion'"'"'s sidewalls on at least two sides of the protrusion;

a floating gate present at least over said sidewalls on at least said two sides of the protrusion and separated from the protrusion by the first dielectric feature;

a second dielectric feature over the floating gate; and

a conductive gate over the second dielectric feature, the conductive gate having a bottom surface coming down along at least the two sides of the protrusion to a level below a top of the protrusion.

9. The integrated circuit of claim 8 wherein:

the protrusion is one of a plurality of protrusions of the semiconductor substrate;

the nonvolatile memory cell is one of a plurality of nonvolatile memory cells in the integrated circuit, each memory cell being associated with a respective one of said protrusions, different protrusions being associated with respective different memory cells of said plurality of memory cells;

wherein each memory cell comprises;

a first dielectric feature on the associated protrusion'"'"'s sidewalls on at least two sides of the associated protrusion;

a floating gate present at least over said sidewalls of the associated protrusion over at least the two sides of the associated protrusion, the floating gate being separated from the associated protrusion by the respective first dielectric feature;

a conductive gate over the second dielectric feature, the conductive gate having a bottom surface coming down along at least the two sides of the associated protrusion to a level below a top of the associated protrusion;

wherein the integrated circuit further comprises a conductive line interconnecting the conductive gates and having a planar top surface lying above the tops of the protrusions.

10. An integrated circuit comprising a nonvolatile memory cell comprising:

a semiconductor substrate having an upward protrusion;

a first dielectric feature present at least on the protrusion'"'"'s sidewalls on at least two sides of the protrusion; and

a floating gate present at least over said sidewalls on at least said two sides of the protrusion and separated from the protrusion by the first dielectric feature, the floating gate having a bottom surface coming down along the at least two sides of the protrusion to a level which is below a top of the protrusion by at least 50% of a height of the protrusion.

11. The integrated circuit of claim 10 wherein said level is below the top of the protrusion by at least 90% of the height of the protrusion.

12. The integrated circuit of claim 10 wherein the nonvolatile memory cell further comprises:

a second dielectric feature over the floating gate; and

a conductive gate over the second dielectric feature,

13. An integrated circuit comprising a nonvolatile memory cell comprising:

a semiconductor substrate having an upward protrusion;

a first dielectric feature present at least on the protrusion'"'"'s sidewalls on at least two sides of the protrusion and coming down along the at least two sides of the protrusion, wherein the first dielectric feature at least as thick at a top of the protrusion as at a level which is below the top of the protrusion by at least 50% of the height of the protrusion; and

a floating gate present at least over said sidewalls on at least said two sides of the protrusion and separated from the protrusion by the first dielectric feature, the floating gate having a bottom surface coming down along the at least two sides of the protrusion and physically contacting the first dielectric feature at least at said level.

14. The integrated circuit of claim 13 wherein the nonvolatile memory cell further comprises:

a second dielectric feature over the floating gate; and

a conductive gate over the second dielectric feature the conductive gate having a bottom surface coming down along at least the two sides of the protrusion to a level at least 50% below the top or the protrusion by at least 50% of the height of the protrusion.