METHOD FOR FABRICATING A HIGH-K DIELECTRIC LAYER

• US 20080265380A1
• Filed: 04/16/2008
• Published: 10/30/2008
• Est. Priority Date: 10/20/2005
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International), Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ragnarsson, Lars-Ake, De Gendt, Stefan, Schram, Tom, Yamamoto, Kazuhiko, Zimmerman, Paul, Vandervorst, Wilfried, Deweerd, Wim, Brunco, David
• Granted Patent: US 8,211,812 B2
• Time in Patent Office: Days
• US Class Current: 257/632
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02159 the material containing zirconium, e.g. ZrSiOx
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/316 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/31637 Deposition of Tantalum oxides, e.g. Ta2O5
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 : Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Claims

1. A method of fabricating a high-k dielectric layer comprising:

depositing onto a substrate a high-k dielectric material so as to form a high-k dielectric layer with a first thickness; and

thinning the high-k dielectric layer to a second thickness to form the high-k dielectric layer having a higher density than is obtained by depositing the high-k dielectric material with the second thickness.

2. The method according to claim 1, wherein the first thickness is selected so that the high-k dielectric layer deposited with the first thickness has a density of at least the bulk density value of the high-k dielectric material minus about 10%.

3. The method according to claim 1, wherein the second thickness is at least ⅕

of the thickness at which a high-k dielectric layer deposited has a density equal to the bulk density value of the high-k dielectric material minus 10%.

4. The method according to claim 3, wherein the second thickness is less than about ½

of the thickness at which a high-k dielectric layer deposited has a density equal to the bulk density value of the high-k dielectric material minus 10%.

5. The method according to claim 3, wherein the second thickness is less than about ⅓

of the thickness at which a high-k dielectric layer deposited has a density equal to the bulk density value of the high-k dielectric material minus 10%.

6. The method according to claim 3, wherein the second thickness is less than about ¼

of the thickness at which a high-k dielectric layer deposited has a density equal to the bulk density value of the high-k dielectric material minus 10%.

7. The method according to claim 1, wherein the thinning of the high-k dielectric layer to a second thickness is performed by etching back the high-k dielectric layer.

8. The method according to claim 7, wherein the etching back of the high-k dielectric layer is performed by a wet etching process.

9. The method according to claim 1, wherein the second thickness is selected such that the high-K dielectric layer of the second thickness has a desired layer quality.

10. The method according to claim 9, wherein the layer quality is defined by at least one of the following parameters:

density, film closure, roughness, and electrical leakage.

11. The method according to claim 1, wherein the high-k dielectric layer is at least one of the following:

a metal oxide, metal silicate, metal oxynitride, and metal silicon oxynitride.

12. The method according to claim 1, wherein the process of depositing the high-k dielectric layer with a first thickness and thinning the high-k dielectric layer to a second thickness are repeated sequentially.

13. The method according to claim 1, wherein the high-k dielectric layer has a k value higher than 3.9.

14. The method according to claim 1, wherein the high-k dielectric layer functions as gate dielectric in a field effect transistor.

15. A high-k dielectric layer formed according to the method of claim 1.

16. The high-k dielectric layer according to claim 15, wherein the high-k dielectric layer has a thickness of less than the thickness of an as-deposited high-k layer whose density equals the bulk density value.

17. The high-k dielectric layer according to claim 15, wherein the high-k dielectric layer has increased density and decreased electrical leakage compared to an as-deposited layer of a same high-k dielectric material of equal thickness.

18. A semiconductor device comprising the high-k dielectric layer according to claim 15.

19. A method of fabricating a high-k dielectric layer comprising:

depositing a high-k dielectric layer of a first thickness, the first thickness is selected so that the high-k dielectric layer deposited has a density of at least the bulk density value of the high-k dielectric material minus about 10%; and

thinning the high-k dielectric layer to a second thickness.

20. A high-k dielectric layer formed according to the method of claim 19.