SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVATION LAYER

• US 20080265413A1
• Filed: 06/04/2008
• Published: 10/30/2008
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming, Lo, Hsin-Jung, Lin, Ching-San
• Granted Patent: US 8,004,092 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05173 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05176 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05673 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05676 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13169 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13173 : Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/13176 : Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/4554 : Coating
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48477 : being a pre-ball (i.e. a ball formed by capillary bonding)
• CPC Class Codes: H01L 2224/4943 : the connecting portions being staggered
• CPC Class Codes: H01L 2224/85051 : Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns

Claims

1. A chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer;

a first contact pad exposed by a first opening in said passivation layer;

a second contact pad exposed by a second opening in said passivation layer;

a third contact pad exposed by a third opening in said passivation layer, wherein said first, second and third contact pads comprise electroplated copper, and wherein said first, second and third contact pads are aligned in a first line, wherein said second contact pad is between said first and third contact pads;

a patterned metal layer over said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a first copper layer having a thickness between 1 and 10 micrometers over said passivation layer and over said first, second and third contact pads, and wherein said patterned metal layer comprises a metal trace over said passivation layer, and a fourth contact pad connected to said second contact pad through said metal trace, wherein the position of said fourth contact pad from a top perspective view is different from that of said second contact pad;

a first metal bump on said patterned metal layer and over said first contact pad;

a second metal bump on said fourth contact pad; and

a third metal bump on said patterned metal layer and over said third contact pad, wherein said first and third metal bumps are aligned in a second line parallel with said first line, wherein said third metal bump comprises a second copper layer directly on said first copper layer, and wherein said third metal bump is used to be connected to a fifth contact pad on a flexible substrate.

2. The chip of claim 1 further comprising a polymer layer between said patterned metal layer and said passivation layer.

3. The chip of claim 2, wherein said polymer layer comprises polyimide.

4. The chip of claim 1, wherein said patterned metal layer further comprises a titanium-containing layer under said first copper layer.

5. The chip of claim 1, wherein said third metal bump further comprises a nickel-containing layer on said second copper layer.

6. The chip of claim 1, wherein said third metal bump further comprises a gold layer over said second copper layer, wherein said gold layer has a height between 1 and 50 micrometers.

7. The chip of claim 1, wherein said third metal bump further comprises a nickel-containing layer on said second copper layer and a gold layer on said nickel-containing layer.

8. The chip of claim 1, wherein said third metal bump further comprises a tin-containing layer over said second copper layer.

9. The chip of claim 1, wherein said third metal bump further comprises a nickel-containing layer over said second copper layer and a tin-containing layer on said nickel-containing layer.

10. A chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer;

a first contact pad exposed by a first opening in said passivation layer;

a second contact pad exposed by a second opening in said passivation layer;

a third contact pad exposed by a third opening in said passivation layer, wherein said first, second and third contact pads are aligned in a first line, wherein said second contact pad is between said first and third contact pads;

a patterned metal layer over said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a first copper layer having a thickness between 1 and 10 micrometers over said passivation layer and over said first, second and third contact pads, and wherein said patterned metal layer comprises a metal trace over said passivation layer, and a fourth contact pad connected to said second contact pad through said metal trace, wherein the position of said fourth contact pad from a top perspective view is different from that of said second contact pad;

a first metal bump on said patterned metal layer and over said first contact pad, wherein said first metal bump comprises a second copper layer directly on said first copper layer and a gold layer over said second copper layer;

a second metal bump on said fourth contact pad;

a third metal bump on said patterned metal layer and over said third contact pad, wherein said first and third metal bumps are aligned in a second line parallel with said first line; and

a first polymer layer over said patterned metal layer.

11. The chip of claim 10 further comprising a second polymer layer between said patterned metal layer and said passivation layer.

12. The chip of claim 11, wherein said second polymer layer comprises polyimide.

13. The chip of claim 10, wherein said patterned metal layer further comprises a titanium-containing layer under said first copper layer.

14. The chip of claim 10, wherein said first metal bump further comprises a nickel-containing layer between said second copper layer and said gold layer.

15. The chip of claim 10, wherein said first and second metal layers comprise electroplated copper.

16. The chip of claim 10, wherein said gold layer has a thickness between 1 and 50 micrometers.

17. A chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer;

a first contact pad exposed by a first opening in said passivation layer;

a second contact pad exposed by a second opening in said passivation layer;

a third contact pad exposed by a third opening in said passivation layer, wherein said first, second and third contact pads comprise electroplated copper, and wherein said first, second and third contact pads are aligned in a first line, wherein said second contact pad is between said first and third contact pads;

a patterned metal layer over said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a first copper layer having a thickness between 1 and 10 micrometers over said passivation layer and over said first, second and third contact pads, and wherein said patterned metal layer comprises a first metal trace over said passivation layer, a fourth contact pad connected to said first contact pad through said first metal trace, wherein the position of said fourth contact pad from a top perspective view is different from that of said first contact pad, a second metal trace over said passivation layer, a fifth contact pad connected to said second contact pad through said second metal trace, wherein the position of said fifth contact pad from said top perspective view is different from that of said second contact pad, a third metal trace over said passivation layer, and a sixth contact pad connected to said third contact pad through said third metal trace, wherein the position of said sixth contact pad from said top perspective view is different from that of said third contact pad, wherein said second metal trace passes through a gap between said fourth and sixth contact pads;

a first metal bump on said fourth contact pad, wherein said first metal bump comprises a second copper layer directly on said first copper layer and a gold layer over said second copper layer;

a second metal bump on said fifth contact pad;

a third metal bump on said sixth contact pad, wherein said first and third metal bumps are aligned in a second line parallel with said first line; and

a first polymer layer over said patterned metal layer.

18. The chip of claim 17 further comprising a second polymer layer between said patterned metal layer and said passivation layer.

19. The chip of claim 17, wherein said patterned metal layer further comprises a titanium-containing layer under said first copper layer.

20. The chip of claim 17, wherein said first metal bump further comprises a nickel-containing layer between said second copper layer and said gold layer.