METHOD FOR PULSE WIDTH MODULATION SYNCHRONIZATION IN A PARALLEL UPS SYSTEM

• US 20080265680A1
• Filed: 02/27/2008
• Published: 10/30/2008
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Vertiv Corporation (Vertiv Holdings Co.)
• Original Assignee: Liebert Corporation (Vertiv Holdings Co.)
• Inventors: ESCHHOFEN, Kevin Kim, MARWALI, Mohammad Nanda Rahmana, HEBER, Brian Paul
• Granted Patent: US 7,667,351 B2
• Time in Patent Office: Days
• US Class Current: 307/65
• CPC Class Codes: H02J 9/062 for AC powered loads
• CPC Class Codes: H02M 7/493 the static converters being arranged for operation in parallel

Abstract

A method for pulse width modulated pulse synchronization in a parallel UPS system uses the locally measured critical bus voltage to detect a zero crossing and adjust the PWM pulse to coincide with the zero crossing. No communication between the units is required to perform synchronization, and no “master” and “slave” relationship exists to thereby increase the total system reliability.

Claims

1. A method for pulse width modulated (PWM) pulse synchronization in a parallel power supply system comprising:

providing at least first and second power supplies connected in parallel, wherein each power supply is connected to a common output bus voltage having a zero voltage crossing, a control update point and a cycle period;

adjusting the control update point and thereby the PWM pulse, such that the PWM pulses coincide with the detected zero voltage crossing so that the PWM pulses are in synchronization across all power supplies in the system.

2. The method of claim 1, wherein the at least first and second power supplies are uninterruptible power supply units (UPS).

3. The method of claim 1 further comprising adjusting the sample rate to a fixed number of PWM pulses in one cycle period of the bus voltage;

4. The method of claim 1 further comprising:

sampling the bus voltage at a predetermined sampling rate;

determining a frequency of the bus voltage;

adjusting the sample rate to a fixed number of PWM pulses in one cycle period of the bus voltage;

detecting a zero voltage crossing of the bus voltage; and

5. The method of claim 4 in which the frequency of the bus voltage is determined from measurement of time between consecutive zero crosses of the output voltage.

6. The method of claim 4 in which the frequency of the bus voltage is determined from an internally generated voltage reference derived from a voltage fed commonly to all UPS units.

7. The method of claim 1 in which the zero voltage crossing of the bus voltage is detected by each controller from an internally generated voltage reference derived from a voltage fed commonly to all UPS units.

8. The method of claim 1 in which adjusting the control update time and thereby the PWM pulse to coincide with the detected zero voltage crossing includes continuously adjusting the PWM pulse frequency based on a phase error (time difference between the control update time and voltage zero cross) and a frequency error (frequency difference between integer multiple of the PWM pulse frequency and the output voltage frequency).

9. The method of claim 8, whereby the rate of change of the adjustment is limited to provide a gradual change of the PWM frequency over time.

11. The system of claim 1, wherein the at least first and second power supplies are uninterruptible power supply units (UPS).

10. A system for pulse width modulated (PWM) pulse synchronization, comprising:

at least first and second power supplies connected in parallel, wherein each power supply is connected to a common output bus voltage having a zero voltage crossing, a control update point and a cycle period,

wherein the control update point is adjusted and thereby the PWM pulse, such that the PWM pulses coincide with the zero voltage crossing so that the PWM pulses are in synchronization across all power supplies in the system.