LINEAR VOLTAGE REGULATING CIRCUIT WITH UNDERSHOOT MINIMIZATION AND METHOD THEREOF

• US 20080265853A1
• Filed: 04/24/2007
• Published: 10/30/2008
• Est. Priority Date: 04/24/2007
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Hung-I, Lou, Chih-Hong
• Granted Patent: US 7,498,780 B2
• Time in Patent Office: Days
• US Class Current: 323/280
• CPC Class Codes: G05F 1/571 with overvoltage detector
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A voltage regulating circuit for providing a regulated output voltage. The voltage regulating circuit includes a voltage regulator, a converting circuit, a capacitive device, a first current mirror module, and a second current mirror module. The voltage regulator has a first output producing the regulated output voltage and a second output producing a pass voltage. The converting circuit converts the pass voltage into a first current and a second current passing through a first converting node and a second converting node respectively, where the first current charges/discharges the capacitive device. The first current mirror module has a first current mirror path coupled to the first converting node and a second current mirror path coupled to the second converting node. The second current mirror module has a first current mirror path coupled to the second converting node and a second current mirror path coupled to the first output.

Claims

1. A voltage regulating circuit for providing a regulated output voltage, comprising:

a voltage regulator having a first output producing the regulated output voltage and a second output producing a pass voltage;

a converting circuit, coupled to the voltage regulator, for converting the pass voltage into a first current and a second current, wherein the converting circuit has a voltage input node coupled to the second output for receiving the pass voltage, a first converting node, and a second converting node, the first current flows through the first converting node, and the second current flows through the second converting node;

a capacitive device coupled to the first converting node;

a first current mirror module comprising a first current mirror path coupled to the first converting node and a second current mirror path coupled to the second converting node; and

a second current mirror module comprising a first current mirror path coupled to the second converting node and a second current mirror path coupled to the first output.

2. The voltage regulating circuit of claim 1 wherein the voltage regulator comprises:

an error amplifier having a first input coupled to a first reference voltage, a second input, and an error output coupled to the second output;

a pass transistor having a gate coupled to the second output, a first electrode coupled to a second reference voltage, and a second electrode coupled to the first output; and

a feedback circuit coupled between the first output and the second input.

3. The voltage regulating circuit of claim 1 wherein the converting circuit further comprises:

a transistor having a gate coupled to the second output, a first electrode coupled to a reference voltage, and a second electrode;

a first current generator, coupled to the first converting node and the second electrode, for generating the first current; and

a second current generator, coupled to the second converting node and the second electrode, for generating the second current.

4. The voltage regulating circuit of claim 3 wherein the first and second current generators are current mirrors having a common diode-connected transistor.

5. The voltage regulating circuit of claim 1 wherein the capacitive device is a single capacitor.

6. The voltage regulating circuit of claim 1 wherein the capacitive device comprises:

a third current mirror module comprising a first current mirror path, and a second current mirror path coupled to the first converting node, wherein a current mirror ratio of the second current mirror path of the third current mirror module to the first current mirror path of the third current mirror module is greater than one;

a capacitor, coupled between the first current mirror path of the third current mirror module and the first converting node; and

a transistor having a gate coupled to the second output, a first electrode coupled to a reference voltage, and a second electrode coupled to the first current mirror path of the third current mirror module.

7. The voltage regulating circuit of claim 6 wherein the transistor is a long-channel transistor.

8. The voltage regulating circuit of claim 1 wherein the converting circuit comprises:

a first transistor having a gate coupled to the second output, a first electrode coupled to a reference voltage, and a second electrode coupled to the first converting node; and

a second transistor having a gate coupled to the second output, a first electrode coupled to the reference voltage, and a second electrode coupled to the second converting node.

9. The voltage regulating circuit of claim 1 wherein the capacitive device comprises:

a third current mirror module comprising a first current mirror path, and a second current mirror path coupled to the first converting node, wherein a current mirror ratio of the second current mirror path of the third current mirror module to the first current mirror path of the third current mirror module is greater than one;

a capacitor, coupled between the first current mirror path of the third current mirror module and the first converting node; and

a transistor having a gate coupled to the first converting node, a first electrode coupled to a reference voltage, and a second electrode coupled to the first current mirror path of the third current mirror module.

10. The voltage regulating circuit of claim 9 wherein the transistor is a long-channel transistor.

11. The voltage regulating circuit of claim 1 wherein the second current is greater than the first current.

12. A method for providing a regulated output voltage, comprising:

(a) providing a voltage regulator having a first output producing the regulated output voltage and a second output producing a pass voltage;

(b) converting the pass voltage into a first current and a second current, and passing the first current and the second current at a first converting node and a second converting node, respectively;

(c) coupling a capacitive device to the first converting node;

(d) coupling a first current mirror path to the first converting node and a second current mirror path to the second converting node, wherein the first current mirror path corresponds to the second current mirror path; and

(e) coupling a third current mirror path to the second converting node and a fourth current mirror path to the first output, wherein the third current mirror path corresponds to the fourth current mirror path.

13. The method of claim 12 wherein step (b) is performed by:

providing a transistor having a gate coupled to the second output;

mirroring a current passing through the first transistor to generate the first current; and

mirroring the current passing through the first transistor to generate the second current.

14. The method of claim 12 wherein the capacitive device is a single capacitor.

15. The method of claim 12 wherein step (c) further comprises:

providing the capacitive device a current mirror module comprising a first current mirror path, and a second current mirror path coupled to the first converting node, wherein a current mirror ratio of the second current mirror path of the current mirror module to the first current mirror path of the current mirror module is greater than one;

providing the capacitive device a capacitor, coupled between the first current mirror path of the current mirror module and the first converting node;

enabling the current mirror module for charging/discharging the capacitor when the regulated output voltage enters a overshoot condition; and

stopping the current mirror module from charging/discharging the capacitor when the regulated output voltage enters an under regulation condition.

16. The method of claim 12 wherein step (b) is performed by:

providing a first transistor, having a gate coupled to the second output, for outputting the first current; and

providing a second transistor, having a gate coupled to the second output, for outputting the second current.

17. The method of claim 16 wherein step (c) further comprises:

providing the capacitive device a current mirror module comprising a first current mirror path, and a second current mirror path coupled to the first converting node, wherein the current mirror ratio of the second current mirror path of the current mirror module to the first current mirror path of the current mirror module is greater than one;

providing the capacitive device a capacitor, coupled between the first current mirror path of the current mirror module and the first converting node;

enabling the current mirror module for charging/discharging the capacitor when the regulated output voltage enters a overshoot condition; and

stopping the current mirror module from charging/discharging the capacitor when the regulated output voltage enters an under regulation condition.

18. The method of claim 12 wherein the second current is greater than the first current.