Leadframe Configuration to Enable Strip Testing of SOT-23 Packages and the Like

• US 20080265923A1
• Filed: 02/06/2008
• Published: 10/30/2008
• Est. Priority Date: 04/27/2007
• Status: Abandoned Application

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Kitnarong, Rangsun, Jarupate, Kanit
• Application Number:
  US12/026,653
• Publication Number:
  US 20080265923A1
• Time in Patent Office: Days
• US Class Current: 324/755
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

A reduced width tie bar and a common lead hold a die paddle of each integrated circuit SOT-23 package to a leadframe within a strip of leadframes after isolating signal leads from the leadframe. Strip testing of most devices in the SOT-23 lead packages may then be performed. The common lead may be at the center of an edge of the SOT-23 package. Also the common lead may be any one of the leads of the SOT-23 package. The reduced width tie bar may be downstream of the epoxy encapsulation flow for better package integrity.

Claims

1. A strip of leadframes configured for strip testing of integrated circuit devices, comprising:

a plurality of leadframes within a strip, each of the plurality of leadframes comprising an integrated circuit device;

each of the integrated circuit devices comprising

a die paddle,

an integrated circuit die attached to a face of the die paddle,

a common lead connected to an edge of the die paddle and to a respective one of the plurality of leadframes,

a reduced width tie bar connected to another edge of the die paddle and to the respective one of the plurality of leadframes,

at least two signal leads electrically coupled to the integrated circuit die, and

the common lead electrically coupled to the integrated circuit die;

wherein the at least two signal leads are electrically isolated from the respective ones of the plurality of leadframes so that each of the plurality of integrated circuit devices can be electrically tested before being removed from the plurality of leadframes within the strip.

2. The strip of leadframes according to claim 1, wherein bond wires couple each integrated circuit die to respective ones of the at least two signal leads and the common lead.

3. The strip of leadframes according to claim 1, further comprising encapsulation of each of the die paddles, the integrated circuit dice, portions of the common leads, portions of the reduced width tie bars, and portions of the at least two signal leads so as to form packages for the plurality of integrated circuit devices.

4. The strip of leadframes according to claim 3, wherein the reduced width tie bars of each of the plurality of integrated circuit devices are downstream of encapsulation flow.

5. The strip of leadframes according to claim 3, wherein the packages are a three lead SOT23 packages.

6. The strip of leadframes according to claim 3, wherein the packages are five lead SOT23 packages.

7. The strip of leadframes according to claim 3, wherein the packages are six lead SOT23 packages.

8. The strip of leadframes according to claim 3, wherein distal ends of the at least two signal leads are separated from the leadframe before testing of the plurality of integrated circuit devices.

9. The strip of leadframes according to claim 3, wherein distal ends of the common leads are separated from the leadframe and the reduced width tie bars are separated from the packages after testing of the plurality of integrated circuit devices.

10. The strip of leadframes according to claim 1, wherein the plurality of leadframes within the strip are formed by stamping.

11. The strip of leadframes according to claim 1, wherein the plurality of leadframes within the strip are formed by etching.

12. The strip of leadframes according to claim 1, wherein the plurality of integrated circuit devices are tested in parallel.

13. The strip of leadframes according to claim 1, wherein the common leads are ground leads.

14. The strip of leadframes according to claim 1, wherein the common leads connect to a power source common.

15. The strip of leadframes according to claim 1, wherein a one of the at least two signal leads is a power lead that connects to a power source voltage.