INTERFACE CIRCUIT

• US 20080265940A1
• Filed: 04/23/2008
• Published: 10/30/2008
• Est. Priority Date: 04/26/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: INOSE, Hiroshi
• Granted Patent: US 8,138,813 B2
• Time in Patent Office: Days
• US Class Current: 326/80
• CPC Class Codes: H03K 19/0175 Coupling arrangements; Interface arrangements interface arrangements for digital computers G06F3/00, G06F13/00

Abstract

An interface circuit according to one aspect of the present invention may includes a receiving circuit operating on a supply voltage lower than a high-level voltage value of an input binary signal, an input level determination circuit generating an input level determination signal having a frequency higher than a frequency of the binary signal and controls whether to output the input level determination signal or not, based on a voltage level of the binary signal, and an AC coupling element connected between an output terminal of the input level determination circuit and an input terminal of the receiving circuit.

Claims

1. An interface circuit comprising:

a receiving circuit operating on a supply voltage lower than a high-level voltage value of an input binary signal;

an input level determination circuit generating an input level determination signal having a frequency higher than a frequency of the binary signal and controls whether to output the input level determination signal or not, based on a voltage level of the binary signal; and

an AC coupling element connected between an output terminal of the input level determination circuit and an input terminal of the receiving circuit.

2. The interface circuit according to claim 1, wherein

the input determination circuit comprises:

an oscillating circuit outputting an AC signal of the predetermined frequency, as the input level determination signal; and

an output control circuit controlling whether to output an output of the oscillating circuit as the input level determination signal or not, based on the binary signal.

3. The interface circuit according to claim 2, wherein the input determination circuit comprises a plurality of the output control circuits according to a number of the receiving circuits.

4. The interface circuit according to claim 1, wherein the receiving circuit comprises a pulse detector that outputs a connection detecting signal based on presence of the input level determination signal.

5. The interface circuit according to claim 1, wherein the receiving circuit comprises a clamp circuit that limits an upper limit value of the input signal.

6. The interface circuit according to claim 5, wherein the clamp circuit is a protective diode connected between an input node of the receiving circuit and a power supply terminal.

7. The interface circuit according to claim 1, wherein the AC coupling element transmits an AC component of the input level determination signal to the receiving circuit through a capacitor.

8. The interface circuit according to claim 1, wherein the AC coupling element transmits an AC component of the input level determination signal to the receiving circuit through a transformer.

9. The interface circuit according to claim 1, wherein the binary signal has first and second logic levels, and a duration of the first logic level and a duration of the second logic level are not fixed.

10. The interface circuit according to claim 1, wherein the binary signal indicates whether or not other device is connected to the interface circuit through a cable.

11. The interface circuit according to claim 1, wherein the binary signal is an HPD signal defined in an HDMI standard or a DVI standard.