SCANNABLE FLIP-FLOP WITH NON-VOLATILE STORAGE ELEMENT AND METHOD

• US 20080265962A1
• Filed: 04/30/2007
• Published: 10/30/2008
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hoefler, Alexander B., Waldrip, Jeffrey W.
• Granted Patent: US 7,560,965 B2
• Time in Patent Office: Days
• US Class Current: 327/202
• CPC Class Codes: G01R 31/318541 Scan latches or cell details

Abstract

A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.

Claims

1. A circuit comprising:

a master latch having an input for receiving an input data signal, and an output;

a slave latch having a first input coupled to the output of the master latch, and an output for providing an output data signal; and

a non-volatile storage element for storing a predetermined value, the non-volatile storage element having an output coupled to the first input of the slave latch, wherein the output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.

2. The circuit of claim 1, wherein the non-volatile storage element comprises one of either a polysilicon fuse or anti-fuse.

3. The circuit of claim 1, wherein the master latch, the slave latch, and the non-volatile storage element form a flip-flop for use in a scan chain comprising a plurality of flip-flops.

4. The circuit of claim 3, wherein the input of the master latch is coupled to an output of a slave latch of a preceding flip-flop of the plurality of flip-flops, and the output of the slave latch is coupled to an input of a master latch of a subsequent flip-flop of the plurality of flip-flops.

5. The circuit of claim 1, wherein the slave latch comprises:

a latching sense amplifier having a storage node for storing a logic state;

a first pass gate having a first current electrode coupled to receive the input data signal, a second current electrode coupled to the storage node, and a control electrode coupled to receive a first control signal; and

a second pass gate having a first current electrode coupled to the output of the non-volatile storage element, a second current electrode coupled to the storage node, and a control electrode for receiving a second control signal.

6. The circuit of claim 5, wherein the latching sense amplifier comprises a pair of cross-coupled inverters coupled to the storage node.

7. The circuit of claim 1, wherein the master latch comprises:

a first inverter having an input terminal coupled to receive the input data signal, and an output terminal; and

a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter, and a control terminal for receiving a clock signal.

8. The circuit of claim 1, wherein the slave latch comprises a pair of cross-coupled inverters coupled between a first storage node and a second storage node, wherein the first and second storage nodes for providing complementary output data signals.

9. The circuit of claim 8, further comprising:

a first pass gate coupled between the first storage node and the output of the non-volatile storage element; and

a second pass gate coupled between the second storage node and a reference element.

10. The circuit of claim 9, wherein the reference element comprises a plurality of series-connected polysilicon fuses.

11. In a plurality of flip-flops, each flip-flop comprising a master latch, a slave latch, and a non-volatile storage element, a method comprising:

asserting a scan enable signal to enable the plurality of flip-flops to scan data;

providing an input data signal to an input of the master latch;

transferring the input data signal from an output of the master latch, through the slave latch, and to an input of a subsequent flip-flop in the plurality of flip-flops;

de-asserting the scan enable signal;

asserting a sense enable signal to couple the non-volatile storage element to the slave latch;

storing a logic state of the non-volatile storage element in the slave latch; and

reading the logic state from the slave latch.

12. The method of claim 11, wherein storing and reading the logic state further comprises both storing the logic state of the non-volatile storage element in the slave latch and reading the logic state from the slave latch in response to a signal transition of the sense enable signal.

13. The method of claim 11, wherein reading the logic state from the slave latch further comprises reading complementary data signals from the slave latch.

14. The method of claim 11, wherein reading the logic state from the slave latch further comprises reading a logic state of the slave latch of each of the plurality of flip-flops, wherein in a first mode the plurality of flip-flops are read in parallel and in a second mode the plurality of flip-flops are read in series.

15. A circuit comprising:

a plurality of flip-flops coupled together, each of the plurality of flip-flops comprising;

a master latch having an input for receiving an input data signal, and an output;

a slave latch comprising a pair of cross-coupled inverters coupled between a first storage node and a second storage node, the first and second storage nodes coupled to the output of the master latch;

a non-volatile storage element for storing a predetermined value, the non-volatile storage element having an output coupled to the first storage node of the slave latch; and

a reference element coupled to the second storage node, wherein the first and second storage nodes provide complementary output data signals corresponding to one of the input data signal or the predetermined value in response to an enable signal.

16. The circuit of claim 15, wherein the non-volatile storage element comprises one of either a polysilicon fuse or anti-fuse.

17. The circuit of claim 15, wherein the slave latch further comprises:

a first pass gate having a first current electrode coupled to the non-volatile storage element, a second current electrode coupled to the first storage node, and a control electrode; and

a second pass gate having a first current electrode coupled to the reference element, a second current electrode coupled to the second storage node, and a control electrode.

18. The circuit of claim 17, wherein the slave latch further comprises:

a third pass gate having a first current electrode coupled to the output of the master latch, a second current electrode coupled to the first storage node, and a control electrode; and

a fourth pass gate having a first current electrode coupled to the output of the master latch, a second current electrode coupled to the second storage node, and a control electrode.

19. The circuit of claim 15, wherein the master latch comprises:

a first inverter having an input terminal coupled to receive the input data signal, and an output terminal; and

a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter, and a control terminal for receiving a clock signal.

20. The circuit of claim 15, wherein the input of the master latch is coupled to an output of a slave latch of a preceding flip-flop of the plurality of flip-flops, and the output of the slave latch is coupled to an input of a master latch of a subsequent flip-flop of the plurality of flip-flops.