Scalable High Performance 3D Graphics

• US 20080266300A1
• Filed: 05/27/2008
• Published: 10/30/2008
• Est. Priority Date: 03/22/2002
• Status: Active Grant

• Current Assignee: Gamehancement LLC (Jeffrey M. Gross)
• Original Assignee: Michael F. Deering
• Inventors: Deering, Michael F., Lavelle, Michael G.
• Granted Patent: US 7,808,505 B2
• Time in Patent Office: Days
• US Class Current: 345/502
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 5/70 Denoising; Smoothing

Abstract

A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Claims

1. A node for use in a 3D graphics hardware accelerator implemented as a plurality of nodes connected to a ring, the node comprising:

a loop interface for receiving packets from a neighboring node on the ring and for transmitting packets to another neighboring node on the ring;

a memory port to a local memory sub-system;

a render stage coupled to the loop interface and to the memory port, the render stage for receiving graphics primitive loop packets via the loop interface, executing the graphics rendering specified in the graphics primitive loop packets including accessing via the memory port a texture store in the local memory sub-system as required by the graphics primitive loop packet, and generating corresponding draw pixel loop packets;

a sample fill stage coupled to the loop interface and to the memory port, the sample fill stage for receiving draw pixel loop packets via the loop interface and, as specified by the draw pixel loop packets, performing via the memory port a conditional sample update function of samples and/or pixels in an interleave of a super-sampled frame buffer stored in the local memory sub-system; and

a video output stage coupled to the loop interface and to the memory port, the video output stage for receiving video pixel loop packets via the loop interface and, as specified by the video pixel loop packets, retrieving via the memory port samples and/or pixels in the interleave stored in the local memory sub-system to modify the video pixel loop packets, and transmitting the modified video pixel loop packets via the loop interface.

2. The node of claim 1, further comprising an interface unit, the interface unit including a host interface for connecting to a host computer, the interface unit receiving graphics driver commands from the host computer and converting the graphics driver commands to loop packets for transmission over the ring to other nodes.

3. The node of claim 2, wherein the interface unit converts the graphics driver commands to graphic commands, assigns the graphics commands to render stages and transmits the graphics commands to the assigned render stages via the loop interface.

4. The node of claim 3, wherein the interface unit that assigns the graphic commands uses a load balancing method.

5. The node of claim 2, wherein the interface unit further receives modified video pixel loop packets via the loop interface and transmits rendered images based thereon to the host computer.

6. The node of claim 2, wherein the interface unit further transmits rendered images to one or more physical images display devices not on the ring.

7. The node of claim 1, wherein the video output stage further performs convolution.

9. The node of claim 1, wherein the render stage includes a clip checking operation.

10. The node of claim 1, wherein the render stage includes a clipping operation if needed.

11. The node of claim 1, wherein the render stage includes vertex shading.

12. The node of claim 1, wherein the render stage includes scan converting.

13. The node of claim 1, wherein the render stage includes programmable shading on vertices.

14. The node of claim 1, wherein the render stage includes programmable shading on pixels.

15. The node of claim 1, wherein the render stage includes programmable shading on micropolygon vertices.

16. The node of claim 1, wherein the render stage includes computation processing including texture operations.

17. The node of claim 1, wherein the render stage includes displacement mapping.

18. The node of claim 1, wherein the render stage includes programmable shading.

19. The node of claim 1, wherein the render stage includes multicasting “

projected to screen space boundaries”

of the results of tessellating and shading graphics primitives to targeted ones of the interconnected nodes, along with the plane equation of Z.

20. The node of claim 1, wherein the texture store contains a rendered image.

21. The node of claim 1, wherein the render stage applies a texture filtering technique to a texture map stored in the local memory sub-system.

22. The node of claim 21, wherein said texture filtering technique includes one or more of direct access, nearest neighbor access, bi-linear filtering, tri-linear filtering, bi-linear MIP mapping, tri-linear MIP mapping, anisotropic filtering, summed area filtering, procedural textures, bump mapping, displacement mapping, percentage closer shadow filtering, and deep shadow map filtering.

23. The node of claim 1, wherein the render stage includes surface tessellation.

24. The node of claim 23, wherein the surface tessellation includes the tessellation of surface primitives.

25. The node of claim 24, wherein the surface primitives include one or more of polygons, higher order surface primitives, and implicit surfaces.

26. The node of claim 25, wherein the higher order surface primitives includes one or more of conic surfaces, ruled surfaces, surfaces of revolution, Bé

zier patches, B-Spline patches, NURBS patches, sub-division surfaces, and sub-division surfaces with edge and vertex sharpness control.

27. The node of claim 23, wherein the tessellation includes the application of displacement maps.

28. The node of claim 1, wherein the node uses a single physical connection for all information transfer on the ring.

29. The node of claim 1, wherein the node uses point to point, unidirectional links for all information transfer on the ring.

30. The node of claim 1, wherein the loop interface, render stage, sample fill stage, video output stage, memory port and local memory sub-system are formed of a single processing chip.

31. The node of claim 1, wherein the loop interface, render stage, sample fill stage, video output stage and memory port are formed of a single processing chip and the local memory sub-system is formed of at least one memory chip.

8. The node of claim 8, wherein the video output stage further performs anti-aliasing.