SRAM CELL CONTROLLED BY FLASH MEMORY CELL

• US 20080266955A1
• Filed: 07/15/2008
• Published: 10/30/2008
• Est. Priority Date: 10/05/2004
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Plants, William C.
• Granted Patent: US 7,558,112 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: H03K 19/1776 for memories

Abstract

First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.

Claims

1. A multi-purpose static random-access-memory cell controllable by a non-volatile memory cell comprising:

a static random-access-memory cell coupled between first and second complimentary static random-access-memory cell bit nodes;

a static random-access-memory cell word line;

first and second complimentary static random-access-memory cell bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit nodes through first and second access transistors, each of the first and second access transistors having a gate coupled to the static random-access-memory cell word line;

a configuration word line;

first and second complimentary configuration bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit nodes through third and fourth access transistors, each of the third and fourth access transistors having a gate coupled to the configuration word line;

a serial shift register stage having first and second complementary clock lines, said serial shift register stage coupled to the first and second complimentary static random-access-memory cell bit nodes;

a non-volatile memory cell having an output;

a complementing transistor coupled to the output of the non-volatile memory;

a first transistor switch coupled between the output of the non-volatile memory cell and the first static random-access-memory cell bit node, the first transistor switch having a gate;

a second transistor switch coupled between the output of the complementing transistor and the second static random-access-memory cell bit node, the second transistor switch having a gate;

a control circuit coupled to the gates of the first and second transistor switches.