VOLTAGE BOOSTER AND MEMORY STRUCTURE USING THE SAME

• US 20080266998A1
• Filed: 08/22/2007
• Published: 10/30/2008
• Est. Priority Date: 04/24/2007
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Chen, Chih-Jen
• Granted Patent: US 7,742,346 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A voltage booster and a memory structure using the same are provided. When a data storage unit in the memory structure is in normal operation, all voltage pumps in the voltage booster are turned on for boosting a supply voltage. However, when the data storage unit is in standby state, in the voltage booster, some voltage pumps are turned on while other voltage pumps are turned off, for boosting the supply voltage. Accordingly, the standby current and power consumption are reduced and the pump efficiency is improved.

Claims

1. A voltage booster, comprising:

at least one first stage voltage pump, comprising a first pump circuit, wherein the first pump circuit transfers electronic charges from a supply voltage to a first node voltage;

at least one second stage voltage pump, coupled to the first stage voltage pump, the second stage voltage pump comprising a second pump circuit, a third pump circuit, and an enabling circuit, wherein the enabling circuit controls on or off states of the third pump circuit according to an active signal, and the second pump circuit transfers electronic charges from the first node voltage to a second node voltage; and

a switch, coupled to the second stage voltage pump;

wherein when the third pump circuit is in normal operation, the third pump circuit transfers electronic charges from the second node voltage to an output voltage, and when the third pump circuit is turned off, the switch conducts the second node voltage as the output voltage, and the current of the output voltage is provided by the second pump circuit.

2. The voltage booster according to claim 1, wherein the first stage voltage pump further comprises:

a first driving circuit, enhancing a first pulse signal and a second pulse signal and outputting the enhanced first pulse signal and the enhanced second pulse signal to the first pump circuit;

a second driving circuit, enhancing a third pulse signal; and

a first coupling element, coupling the third pulse signal enhanced by the second driving circuit to the first node voltage in order to boost the first node voltage.

3. The voltage booster according to claim 2, wherein the second stage voltage pump further comprises:

a third driving circuit, enhancing the first pulse signal and the second pulse signal and outputting the enhanced first pulse signal and the enhanced second pulse signal to the second pump circuit;

a first logic gate, determining whether or not to output the third pulse signal according to the active signal;

a fourth driving circuit, coupled to the first logic gate and enhancing the third pulse signal output by the first logic gate; and

a second coupling element, coupling the third pulse signal enhanced by the fourth driving circuit to the second node voltage in order to boost the second node voltage.

4. The voltage booster according to claim 3, wherein the enabling circuit comprises:

a second logic gate, determining whether or not to output the third pulse signal according to the active signal; and

a third logic gate, determining whether or not to output a fourth pulse signal according to the active signal.

5. The voltage booster according to claim 4, wherein the second stage voltage pump further comprises:

a fifth driving circuit, coupled to the second logic gate and the third logic gate, the fifth driving circuit enhancing the third pulse signal and the fourth pulse signal output by the second logic gate and the third logic gate and outputting the third pulse signal and the fourth pulse signal to the third pump circuit.

6. The voltage booster according to claim 1, wherein the switch comprises a transistor.

7. A memory structure, comprising:

a first voltage booster, generating a first reference voltage, the first voltage booster comprising a plurality of voltage pumps;

a second voltage booster, generating a second reference voltage;

a control circuit, generating an enabling signal according to an address signal and an active signal;

a word line driving circuit, boosting the voltage level of the enabling signal to the first reference voltage or the second reference voltage according to the logic state of the enabling signal; and

a data storage unit, being operated according to the enabling signal boosted by the word line driving circuit;

wherein when the data storage unit is in standby state, a portion of the voltage pumps are turned off in order to reduce a standby current of the memory structure.

8. The memory structure according to claim 7, wherein the voltage pumps of the first voltage booster comprise:

at least one first stage voltage pump, comprising a first pump circuit, wherein the first pump circuit transfers electronic charges from a supply voltage to a first node voltage;

at least one second stage voltage pump, coupled to the first stage voltage pump, the second stage voltage pump comprising a second pump circuit, a third pump circuit, and an enabling circuit, wherein the enabling circuit controls on or off states of the third pump circuit according to an active signal, and the second pump circuit transfers electronic charges from the first node voltage to a second node voltage; and

a switch, coupled to the second stage voltage pump;

wherein when the third pump circuit is in normal operation, the third pump circuit transfers electronic charges from the second node voltage to an output voltage, and when the third pump circuit is turned off, the switch conducts the second node voltage as the output voltage, and the current of the output voltage is provided by the second pump circuit.

9. The memory structure according to claim 8, wherein the first stage voltage pump further comprises:

a first driving circuit, enhancing a first pulse signal and a second pulse signal and outputting the enhanced first pulse signal and the enhanced second pulse signal to the first pump circuit;

a second driving circuit, enhancing a third pulse signal; and

a first coupling element, coupling the third pulse signal enhanced by the second driving circuit to the first node voltage in order to boost the first node voltage.

10. The memory structure according to claim 9, wherein the second stage voltage pump further comprises:

a third driving circuit, enhancing the first pulse signal and the second pulse signal and outputting the enhanced first pulse signal and the enhanced second pulse signal to the second pump circuit;

a first logic gate, determining whether or not to output the third pulse signal according to the active signal;

a fourth driving circuit, coupled to the first logic gate, and enhancing the third pulse signal output by the first logic gate; and

a second coupling element, coupling the third pulse signal enhanced by the fourth driving circuit to the second node voltage in order to boost the second node voltage.

11. The memory structure according to claim 10, wherein the enabling circuit comprises:

a second logic gate, determining whether or not to output the third pulse signal according to the active signal; and

a third logic gate, determining whether or not to output a fourth pulse signal according to the active signal.

12. The memory structure according to claim 11, wherein the second stage voltage pump further comprises:

a fifth driving circuit, coupled to the second logic gate and the third logic gate, the fifth driving circuit enhancing the third pulse signal and the fourth pulse signal output by the second and the third logic gate and outputting the enhanced third pulse signal and the enhanced fourth pulse signal to the third pump circuit.

13. The memory structure according to claim 7, wherein the switch comprises a transistor.