SYNCHRONIZING CIRCUIT AND CONTROLLING METHOD THEREOF

• US 20080267336A1
• Filed: 04/25/2008
• Published: 10/30/2008
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: OKAMOTO, Ikko
• Granted Patent: US 8,155,257 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03D 3/009 Compensating quadrature phase or amplitude imbalances
• CPC Class Codes: H04L 2027/0028 at passband only
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0069 Loop filters
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657

Abstract

Disclosed herein is synchronizing circuit including: a numerically controlled oscillating section; a phase rotating section; a phase error estimating section; a loop filter; and a gain controlling section; wherein the gain controlling section controls the gain so as to suppress an effect of a phase error in an immediate main signal section in a known start section from a start of the known section to a predetermined symbol.

Claims

1. A synchronizing circuit comprising:

numerically controlled oscillating means for generating a signal of a predetermined phase;

phase rotating means for rotating a phase of a symbol of a demodulated signal obtained by demodulating a modulated signal resulting from digital modulation of a carrier according to the signal of said predetermined phase, said demodulated signal including an I-component in phase with said carrier and a Q-component orthogonal to said carrier;

phase error estimating means for estimating a phase error from the rotated phase of the symbol of said demodulated signal;

a loop filter for filtering said phase error and controlling said numerically controlled oscillating means according to a result of the filtering; and

gain controlling means for controlling a gain of said loop filter in symbol units of said demodulated signal, the symbol units forming one of a known section as a section of known symbols and a main signal section as a section of main signal symbols;

wherein said gain controlling means controls said gain so as to suppress an effect of a phase error in an immediate main signal section in a known start section from a start of said known section to a predetermined symbol.

2. The synchronizing circuit according to claim 1,

wherein said gain controlling means controls said gain such that 0 is added as a value of the phase error in said immediate main signal section to a value retained at a time of filtering by said loop filter in said known start section.

3. The synchronizing circuit according to claim 1, further comprising:

phase error average calculating means for calculating an average value of the phase error in said known start section; and

adding means for adding the calculated said average value to a phase correction quantity as output of said loop filter;

wherein said gain controlling means controls said gain such that phase error correction in said known start section is stopped in said loop filter,

said adding means adds said average value to said phase correction quantity when the symbol of said demodulated signal becomes the predetermined symbol, and

said numerically controlled oscillating means generates the signal of said predetermined phase according to the phase correction quantity to which said average value is added.

4. The synchronizing circuit according to claim 1, further comprising

phase error average calculating means for calculating an average value of the phase error in said known start section,

wherein said phase error estimating means estimates said phase error from a difference between the phase of the symbol of said demodulated signal and a phase obtained by adding the calculated said average value to an ideal signal point when the symbol of said demodulated signal becomes said predetermined symbol,

said gain controlling means controls said gain such that phase error correction in said known start section is stopped in said loop filter, and

said loop filter subjects the estimated phase error to filtering and controls said numerically controlled oscillating means according to a result of the filtering.

5. The synchronizing circuit according to claim 1,

wherein said main signal section is a data section, and

said known section is a frame header and a pilot signal when the pilot signal is inserted and is a frame header when the pilot signal is not inserted.

6. A control method of a synchronizing circuit, said synchronizing circuit including numerically controlled oscillating means for generating a signal of a predetermined phase, phase rotating means for rotating a phase of a symbol of a demodulated signal obtained by demodulating a modulated signal resulting from digital modulation of a carrier according to the signal of said predetermined phase, said demodulated signal including an I-component in phase with said carrier and a Q-component orthogonal to said carrier, phase error estimating means for estimating a phase error from the rotated phase of the symbol of said demodulated signal, a loop filter for filtering said phase error and controlling said numerically controlled oscillating means according to a result of the filtering, and gain controlling means for controlling a gain of said loop filter in symbol units of said demodulated signal, said symbol units forming one of a known section as a section of known symbols and a main signal section as a section of main signal symbols, said control method comprising the step of:

controlling said gain so as to suppress an effect of a phase error in an immediate main signal section in a known start section from a start of said known section to a predetermined symbol.