Flash memory device and method of fabricating the same

• US 20080268592A1
• Filed: 12/21/2007
• Published: 10/30/2008
• Est. Priority Date: 03/12/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yong-Tae, Han, Jeong-Uk, Park, Weon-Ho
• Application Number:
  US12/004,698
• Publication Number:
  US 20080268592A1
• Time in Patent Office: Days
• US Class Current: 438/253
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer.

Claims

1. A method of fabricating a flash memory device, comprising:

forming a first dielectric layer on an active region of a semiconductor substrate;

forming a first conductive layer on the first dielectric layer;

forming a mask pattern on the first conductive layer;

etching the first conductive layer using the mask pattern as an etch mask to form a first conductive pattern narrowing from its upper surface toward its middle portion;

forming a second dielectric layer on the semiconductor substrate having the first conductive pattern; and

on the semiconductor substrate having the second conductive layer, forming a second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern.

2. The method according to claim 1, wherein the first conductive layer contains implanted atoms.

3. The method according to claim 2, wherein the concentration of the implanted atoms in the first conductive layer increases from an upper surface of the first conductive layer toward a middle portion of the first conductive layer.

4. The method according to claim 3, wherein the concentration of the implanted atoms in the first conductive layer decreases from the middle portion of the first conductive layer toward a bottom of the first conductive layer.

5. The method according to claim 2, wherein forming the first conductive layer comprises:

forming an undoped silicon layer on the semiconductor substrate having the first dielectric layer; and

implanting first impurity ions into the undoped silicon layer to form a silicon layer containing the implanted atoms.

6. The method according to claim 2, further comprising:

after forming the second conductive pattern, performing a thermal process so that the implanted atoms are diffused and uniformly distributed into the first conductive pattern.

7. The method according to claim 2, wherein the implanted atoms comprise at least one of phosphorus (Ph) and arsenic (As).

8. The method according to claim 1, wherein the first conductive pattern is widened from its middle portion to its bottom.

9. The method according to claim 1, wherein the first conductive pattern is formed to have concave sidewalls.

10. The method according to claim 1, wherein the first conductive layer is etched using a dry etch process.

11. The method according to claim 1, further comprising:

forming a first photoresist pattern having a first opening exposing a portion of the active region adjacent to the first conductive pattern on the semiconductor substrate having the second conductive pattern;

implanting impurity ions into the active region exposed through the first opening using the first photoresist pattern as an ion implantation mask to form a first impurity region;

removing the first photoresist pattern; and

performing a first annealing process for activating the impurity ions implanted into the first impurity region.

12. The method according to claim 11, further comprising:

forming a second photoresist pattern having a second opening exposing the active region adjacent to the second conductive pattern on the semiconductor substrate having the second conductive pattern;

implanting impurity ions into the active region exposed through the second opening using the second photoresist pattern as an ion implantation mask to form a second impurity region;

removing the second photoresist pattern; and

performing a second annealing process for activating the impurity ions implanted into the second impurity region.

13. The method according to claim 12, wherein the second annealing process is performed at a lower temperature than the first annealing process.

14. A flash memory device, comprising:

a first conductive pattern disposed on an active region of a semiconductor substrate, the first conductive pattern having a flat upper surface and narrowing from its upper surface toward its middle portion;

a first dielectric layer interposed between the first conductive pattern and the active region;

a second conductive pattern crossing the active region adjacent to the first conductive pattern and overlapping the first conductive pattern; and

a second dielectric layer having a portion interposed between the second conductive pattern and the first conductive pattern and another portion interposed between the second conductive pattern and the active region.

15. The flash memory device according to claim 14, wherein the first conductive pattern is formed of a doped silicon layer.

16. The flash memory device according to claim 14, wherein the second conductive pattern covers sidewalls of the first conductive pattern while partially overlapping the upper surface of the first conductive pattern.

17. The flash memory device according to claim 14, wherein the first conductive pattern is spaced apart from the second conductive pattern by the thickness of the second dielectric layer.

18. The flash memory device according to claim 14, wherein the first conductive pattern is widened from its middle portion to its bottom.

19. The flash memory device according to claim 14, wherein the first conductive pattern has concave sidewalls.

20. The flash memory device according to claim 14, further comprising:

a first impurity region disposed in the active region adjacent to the first conductive pattern; and

a second impurity region disposed in the active region adjacent to the second conductive pattern,

wherein the second impurity region is a shallower junction than the first impurity region.