SEMICONDUCTOR DEVICE HAVING SILICIDE LAYERS AND METHOD OF FABRICATING THE SAME

• US 20080268598A1
• Filed: 07/03/2008
• Published: 10/30/2008
• Est. Priority Date: 01/02/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOI, Jeong-Min, HA, Tae-Hong
• Granted Patent: US 7,723,194 B2
• Time in Patent Office: Days
• US Class Current: 438/294
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823443 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insulation layer is formed on the isolation layer and on a portion of the active region neighboring the isolation layer. A silicide layer is formed on source/drain regions between the blocking insulation layer and the sidewall spacers. Some embodiments include defining an active region of a substrate using an isolation layer, forming a gate pattern on the active region, implanting impurities into the active region, and forming a spacer insulation layer on a surface of the substrate with the gate pattern. A region of the spacer insulation layer becomes thinner the closer it is to the gate pattern. Other embodiments are described in the claims.

Claims

1. A method of fabricating semiconductor devices comprising:

forming a isolation layer in a semiconductor substrate to define an active region;

forming a gate pattern on the active region;

implanting impurities into the active region at both sides of the gate pattern;

forming a spacer insulation layer on a surface of the semiconductor substrate with the gate pattern, the spacer insulation layer having a first region between the isolation layer and the gate pattern, wherein the closer the first region lies to the gate pattern, the thinner it becomes;

anisotropically etching the spacer insulation layer to form a sidewall spacer on a sidewall of the gate pattern, and to leave a blocking insulation layer on the isolation layer and on a portion of the active region neighboring the isolation layer; and

applying a silicidation process to the semiconductor substrate to form a silicide layer on a source/drain region between the blocking insulation layer and the sidewall spacer, the silicide layer having a boundary aligned to the edge of the blocking insulation layer and a boundary aligned to the edge of the sidewall spacer.

2. The method of claim 1, wherein forming the spacer insulation layer comprises:

stacking a silicon nitride layer and a silicon oxide layer, wherein the first region includes at least one of the silicon nitride layer and the silicon oxide layer.

3. The method of claim 2, wherein anisotropically etching the spacer insulation layer to form the sidewall spacer comprises:

anisotropically etching the silicon oxide layer to form an outer spacer having a curved sidewall on a side of a gate electrode; and

etching the silicon nitride layer using the outer spacer as an etch stop layer to form an inner spacer having an L-shaped cross-section between the outer spacer and the gate pattern.

4. The method of claim 1, wherein forming the spacer insulation layer comprises:

conformally forming a silicon nitride layer on the semiconductor substrate; and

forming a silicon oxide layer on the silicon nitride layer, wherein the first region comprises the silicon oxide layer.

5. The method of claim 4, wherein anisotropically etching the spacer insulation layer comprises:

anisotropically etching the silicon oxide layer to form an outer spacer on a sidewall of the gate pattern and to form a blocking oxide layer on the isolation layer and on a portion of the active region neighboring the isolation layer; and

etching the silicon nitride layer using the outer spacer and the blocking oxide layer as an etch mask to form an inner spacer interposed between the outer spacer and the gate pattern and to form a blocking nitride layer under the blocking oxide layer.

6. The method of claim 1, wherein forming the spacer insulation layer comprises:

forming a silicon nitride layer on the semiconductor substrate, wherein the first region comprises the silicon nitride layer; and

conformally forming a silicon oxide layer on the silicon nitride layer.

7. The method of claim 6, wherein anisotropically etching the spacer insulation layer comprises:

anisotropically etching the silicon oxide layer to form an outer spacer on the sidewall of the gate pattern; and

etching the silicon nitride layer using the outer spacer as an etch mask to form a blocking nitride layer on the isolation layer and on a portion of the active region neighboring the isolation layer.

8. The method of claim 1, wherein anisotropically etching the spacer insulation layer comprises:

etching the spacer insulation layer on the active region neighboring the gate pattern is etched at a faster rate than the spacer insulation layer on the active region neighboring the field insulation layer.