SERIALIZATION OF DATA FOR MULTI-CHIP BUS IMPLEMENTATION

• US 20080270650A1
• Filed: 04/27/2007
• Published: 10/30/2008
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: BRACAMONTES DEL TORO, Rocendo
• Granted Patent: US 7,814,250 B2
• Time in Patent Office: Days
• US Class Current: 710/105
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device.

Claims

1. A system including bus communication, the system comprising:

a matrix operative to select destinations for information on buses connected to the matrix;

a first serializer coupled to the matrix and provided on a first device, the first serializer operative to serialize information received from the matrix and send the serialized information over a communication bus; and

a second serializer provided on a second device and coupled to the communication bus, the second serializer operative to receive the serialized information and deserialize the serialized information, wherein the deserialized information is provided to a peripheral provided on the second device.

2. The system of claim 1 wherein the first device is a first integrated circuit chip and the second device is a second integrated circuit chip.

3. The system of claim 1 wherein the peripheral provided on the second device is a master operative to read and write information from and to a slave of the system.

4. The system of claim 1 wherein the peripheral provided on the second device is a slave operative to receive information from and provide information to a master of the system.

5. The system of claim 4 wherein the slave is an Advanced High-performance Bus (AHB) slave that communicates via an AHB protocol.

6. The system of claim 4 wherein the slave is an Advanced Peripheral Bus (APB) slave that communicates via an APB protocol.

7. The system of claim 6 further comprising an AHB/APB bridge provided on the first device, the AHB/APB bridge being enhanced to permit wait cycles in communications over the communication bus to allow the serialization of the information.

8. The system of claim 1 wherein the first and second serializers each include a mechanism operative to introduce automatic wait cycles in the communication protocol for the communication bus to allow the serialization of the information.

9. The system of claim 8 wherein the automatic wait cycles are based at least in part on a ratio between a serial clock and a system clock frequencies.

10. The system of claim 1 further comprising at least one additional device including a peripheral, wherein a serializer coupled to the matrix is provided on the first device and is connected to a serializer on the additional device by a communication bus, the serializer on the additional device being coupled to the peripheral.

11. A method for providing bus communication, the method comprising:

serializing bus information received from a matrix using a first serializer provided on a first device and sending the serialized bus information over a communication bus; and

receiving the serialized bus information from the communication bus and deserializing the serialized bus information using a second serializer provided on a second device, wherein the deserialized information is provided to a peripheral provided on the second device.

12. The method of claim 11 wherein the peripheral provided on the second device is a master operative to read and write information from and to a slave of the system.

13. The method of claim 11 wherein the peripheral provided on the second device is a slave operative to receive information from and provide information to a master of the system.

14. The method of claim 13 wherein the slave is an AHB slave that communicates via an AHB protocol.

15. The method of claim 13 wherein the slave is an APB slave that communicates via an APB protocol.

16. The method of claim 15 wherein an enhanced AHB/APB bridge provided on the first device permits wait cycles in communications over the communication bus to allow the serialization of the information.

17. The method of claim 11 the first and second serializers introduce automatic wait cycles in the communication protocol for the communication bus to allow the serialization of the information.

18. The method of claim 17 wherein the automatic wait cycles are based at least in part on a ratio between a serial clock and a system clock frequencies.

19. A system including bus communication, the system comprising:

a matrix operative to select destinations for information on multiple buses connected to the matrix, wherein the matrix is provided on a first chip;

a first serializer coupled to the matrix and provided on the first chip, the first serializer operative to serialize information received from the matrix and send the serialized information over a communication bus;

a second serializer provided on a second chip and coupled to the communication bus, the second serializer operative to receive the serialized information and deserialize the serialized information; and

a peripheral coupled to the second serializer and provided on the second chip,

wherein the peripheral receives the deserialized information from the second serializer,

wherein the first and second serializers introduce automatic wait cycles in the communication protocol for the communication bus to allow for the serialization of the information.

20. The system of claim 19 wherein the peripheral is a master operative to read and write information from and to a slave of the system.

21. The system of claim 19 wherein the peripheral is a slave operative to receive information from and provide information to a master of the system.

22. The system of claim 21 wherein the slave is an AHB slave that communicates via an AHB protocol.

23. The system of claim 21 wherein the slave is an APB slave that communicates via an APB protocol, and further comprising an AHB/APB bridge provided on the first device, the AHB/APB bridge being enhanced to permit wait cycles in communications over the communication bus to allow the serialization of the information.

24. A computer readable medium including program instructions to be implemented by a computer and for providing bus communication, the program instructions for:

serializing bus information received from a matrix using a first serializer provided on a first device and sending the serialized bus information over a communication bus; and

receiving the serialized bus information from the communication bus and deserializing the serialized bus information using a second serializer provided on a second device, wherein the deserialized information is provided to a peripheral provided on the second device.