COMMAND RESEQUENCING IN MEMORY OPERATIONS

• US 20080270678A1
• Filed: 04/25/2007
• Published: 10/30/2008
• Est. Priority Date: 04/25/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornwell, Michael J., Dudte, Christopher P., Colligan, Thomas R.
• Granted Patent: US 7,996,599 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution.

Claims

1. A method for managing memory comprising:

receiving command signals for performing flash memory access operations in a first sequence;

determining one or more attributes of one or more of the command signals;

determining a second sequence of execution for the command signals based at least partially on at least one of the attributes; and

executing the command signals in the second sequence to perform access operations on a flash memory.

2. The method of claim 1 wherein at least one of the command signals comprises a read command.

3. The method of claim 2 further comprising promoting at least one read command from the first sequence over at least one write command to produce the second sequence.

4. The method of claim 1 wherein at least one of the command signals includes a write command.

5. The method of claim 1 wherein at least one of the attributes includes an execution time.

6. The method of claim 5 further comprising promoting a command signal with a shorter execution time over a command signal with a longer execution time to produce the second sequence.

7. The method of claim 1 further comprising:

determining if two or more of the command signals are related; and

positioning the related command signals sequentially in the second sequence of execution.

8. The method of claim 7 further comprising consolidating one or more of the related command signals.

9. The method of claim 7 wherein command signals are related when the signals are to the same block of a memory.

10. The method of claim 7 wherein the command signals are related when the signals are related to the same task.

11. The method of claim 1 wherein receiving command signals comprises receiving command signals via a serial ATA bus.

12. The method of claim 1 wherein at least one of the attributes includes time lapsed from receipt of a command signal, and wherein the second sequence may be determined at least partially based on the time lapsed from receipt of the command signal.

13. An article comprising a machine-readable medium storing instructions storing instructions for memory management, the instructions operable to cause data processing apparatus to perform operations comprising:

detecting a first sequence of command signals for performing memory access operations on electrically erasable memory;

determining one or more attributes of one or more of the command signals;

determining a second sequence of execution for one or more of the command signals based at least partially on at least one of the attributes.

14. The article of claim 13 wherein the instructions are further operable to cause data processing apparatus to perform operations comprising executing one or more of the command signals in the second sequence of execution.

15. The article of claim 13 wherein at least one of the command signals includes a read command and the machine-readable medium further stores instructions operable to cause data processing apparatus to perform operations comprising promoting at least one read command over another type of command to generate the second sequence of execution.

16. The article of claim 13 wherein the instructions are further operable to cause data processing apparatus to perform operations comprising:

identifying related command signals; and

positioning related command signals sequentially in the second sequence.

17. The article of claim 13 wherein the instructions are further operable to cause data processing apparatus to perform operations comprising:

identifying at least two command signals operable on a block of a memory;

identifying the relationship between the at least two command signals;

modifying at least one of the related command signals based on the identified relationship.

18. The article of claim 13 wherein the instructions are further operable to cause data processing apparatus to perform operations comprising:

identifying related command signals; and

resolving a conflict between the related command signals, if a conflict between two or more of the related command signals exists.

19. The article of claim 13 wherein at least one of the attributes of one or more of the command signals includes time elapsed since receipt of a command signal, and wherein the second sequence of execution for one or more of the command signals is determined at least partially based on time elapsed since receipt of the command signal.

20. A system comprising:

a first memory operable to store command signals for performing flash memory access operations on a second memory;

a memory controller operable to;

execute one or more of the command signals on the second memory;

determine one or more attributes of one or more of the command signals; and

determine a sequence of execution for one or more of the command signals based at least partially on at least one of the attributes.

21. The system of claim 20 further comprising a serial ATA bus operable to transmit command signals to the memory controller.

22. The system of claim 20 wherein the first memory includes a buffer.

23. The system of claim 20 wherein the second memory comprises an electrically erasable memory.

24. The system of claim 20 further comprising an algorithm configured to assigns weights to command signals based on determined attributes and determine the sequence of execution for one or more of the command signals based on the assigned weights, and wherein the memory controller is configured to execute the algorithm.

25. A system comprising:

means for receiving command signals for performing memory access operations in a first sequence on an electrically erasable memory;

means for determining one or more attributes of one or more of the command signals; and

means for determining a second sequence of execution for one or more of the command signals based at least partially on at least one of the attributes.