Controller for Non-Volatile Memories and Methods of Operating the Memory Controller

• US 20080270680A1
• Filed: 11/13/2006
• Published: 10/30/2008
• Est. Priority Date: 11/17/2005
• Status: Active Grant

• Current Assignee: Chee Keng Chang
• Original Assignee: Chee Keng Chang
• Inventors: Chang, Chee Keng
• Granted Patent: US 8,041,884 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address

Abstract

A non-volatile memory system (3) is proposed consisting of a first non-volatile flash memory (5) having a plurality of blocks, each block having a plurality of pages, each block being erasable and each page being programmable, and a second non-volatile random access memory (23) having a plurality of randomly accessible bytes. The second non-volatile memory (23) stores data for mapping logical blocks to physical blocks and status information of logical blocks. Each logical block has an associated physical page pointer stored in the second non-volatile memory (23) that identifies the next free physical page of the mapped physical block to be written. The page pointer is incremented after every page write to the physical block, allowing all physical pages to be fully utilized for page writes. Furthermore, a method of writing and reading data is disclosed whereby the most recently written physical page associated with a logical address is identifiable by the memory system without programming flags into superseded pages, or recording time stamp values in any physical page or block of the first non-volatile memory (5). Furthermore, a method is provided for a logical block to be mapped to two physical blocks instead of one to provide additional space for page writes, resulting in reduction in page copy operations, thereby increasing the performance of the system.

Claims

1. A memory system having:

a non-volatile solid-state memory for storing user data, the non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,

a mapping data memory arranged to store;

(i) first mapping data indicating, for each of a plurality of logical blocks, a mapping between each logical block and a corresponding first one of said physical blocks;

(ii) for each logical block, a respective first page pointer for indicating a page of the corresponding first physical block, and

(iii) second mapping data indicating for each logical page of each logical block, the physical page of the corresponding first physical block to which data in respect of that logical page was last written; and

a memory controller arranged to perform a write operation in relation to any logical page of any of said logical blocks, said write operation in relation to any given logical page including the steps of;

(a) using the respective first page pointer to identify a physical page of the corresponding first physical block,

(b) writing data to the identified physical page,

(c) updating the second mapping data to indicate the identified physical page as the physical page to which data in respect of the given logical page was last written; and

(d) updating the respective first page pointer to indicate a new physical page of the corresponding first physical block.

2. A memory system according to claim 1 wherein the memory controller is arranged in said write operation to perform an additional step (e) of writing in said identified physical page data indicating the identity of the given logical page.

4. A memory system according to claim 1, in which at least a portion of said mapping data memory is stored in a random access memory.

5. A memory system according to claim 1 in which at least a portion of said mapping data memory is stored in a non-volatile random access memory.

6. A memory system according to claim 1 in which at least a portion of said mapping data memory is within said non-volatile solid state memory.

7. A memory system according to claim 1 wherein the mapping data memory is arranged to store:

a table having a plurality of entries, wherein each entry is uniquely addressable by and associated with a logical block, and wherein each entry has a field for registering said page pointer.

8. A memory system according to claim 1 wherein the mapping data memory is arranged to store:

a table having a plurality of entries, wherein each entry is uniquely addressable by and associated with a logical block, and wherein each entry has a field for registering said corresponding first physical block.

9. A memory system according to claim 8 when dependent on claim 7 wherein said page pointer and said fields are portions of a single first table.

10. A memory system according to claim 8 when dependent on claim 5 wherein the first table is stored in the non-volatile random access memory.

11. A memory system according to claim 9 or claim 10 in which each said entry further includes a first tag for indicating whether the corresponding logical block is associated with a first physical block.

3. A memory system having:

a non-volatile solid-state memory for storing user data, the non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,

a mapping data memory arranged to store;

(i) first mapping data indicating, for each of a plurality of logical blocks, a mapping between each logical block and a corresponding first one of said physical blocks;

(ii) for each logical block, a respective first page pointer for indicating a page of the corresponding first physical block, and

a memory controller arranged to perform a write operation in relation to any logical page of any of said logical blocks, said write operation in relation to any given logical page including the steps of;

(a) using the respective first page pointer to identify a physical page of the corresponding first physical block,

(b) writing user data to the identified physical page,

(c) writing in said identified physical page identity data indicating the identity of the given logical page; and

(d) updating the pointer according to a predefined sequence;

whereby the user data and identity data written to said identified physical page supersede any user data and identity data in a physical page of the corresponding first physical block previously associated with the logical page.

12. A memory system having:

a first non-volatile memory for storing user data, the first non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,

a second memory, the second memory being organized into a plurality of bytes, the bytes being randomly accessible, each byte being writable and readable as a unit, the second memory being arranged to store data mapping logical blocks to corresponding physical blocks;

a memory controller arranged to store user data in said first non-volatile memory;

at least a portion of the second memory being non-volatile, at least a portion of the mapping data being stored in said non-volatile memory.

13. A memory system according to claim 12, the second memory being arranged to store:

a table comprising a plurality of entries, wherein each entry is uniquely addressable by and associated with a physical block number, and each entry records a usage status of a respective associated physical block of first non-volatile memory.

14. A memory system according to claim 13, wherein the said status takes at least four states:

a first state indicating the physical block is erased and free for allocation,

a second state indicating the physical block is currently being mapped to a logical block and used for storing user data,

a third state indicating the physical block is ready for erasure, and

a fourth state indicating the physical block is not fit for read or write.

15. A memory system according to claim 14,

a memory controller arranged to write pages of said physical blocks of first non-volatile memory for storing user data, and at certain times erasing one or more of said physical blocks, upon which the erased blocks are free for allocation, the steps of updating an entry of said fourth table in second non-volatile memory of an associated physical block, including:

from first state to second state when said physical block is allocated for writing data,

from second state to third state when said physical block is de-allocated for writing data,

from third state to first state when said physical block has been erased from any state to fourth state when writing or erasing said physical block returns an error condition.

16. A memory system having:

a non-volatile solid-state memory for storing user data, the non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,

a mapping data memory storing data indicating, for each of a plurality of logical blocks, a mapping between the logical blocks and corresponding first ones of physical blocks;

a memory controller arranged to perform a write operation in relation to any logical page of any of said logical blocks, said write operation comprising storing data relating to a said logical page of a said logical block in a physical page of the corresponding first physical block,

said memory controller being arranged, upon a physical block fullness criterion being met in respect of the first physical block, to associate a second physical block with the corresponding logical block, and subsequently to write data relating to logical pages of that logical block in pages of the second physical block.

17. A memory system according to claim 16 in which at least a portion of said mapping data memory is a random access memory.

18. A memory system according to claim 17 in which at least a portion of said mapping data memory is a non-volatile random access memory.

19. A memory system according to any of claims 16 to 18 in which said physical block fullness criterion is that all pages of said first physical block have been written to.

20. A memory system having:

a non-volatile memory for storing user data, the non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,

a mapping data memory arranged to store;

(i) first mapping data indicating, for each of the plurality of logical blocks, a mapping between each logical block and a corresponding first one of said physical blocks;

(ii) third mapping data indicating, for at least one of the plurality of logical blocks, a mapping between the or each logical block and a corresponding second one of said physical blocks;

a memory controller arranged to perform a write operation into the non-volatile solid-state memory of user data in relation to any specified one of the plurality of logical blocks,

said write operation including, in the case of a logical block which is one of said at least one logical blocks, writing user data into a determined one of the corresponding first and second physical blocks.

21. A memory system according to claim 20 in which said write operation including, in the case of a logical block which is one of said at least one logical blocks, the steps of:

(a) determining if a fullness criterion in respect of first physical block is met;

(b) if determination in (a) is negative, identifying a physical page of the corresponding first physical block;

(c) if determination in (a) is positive, identifying a physical page of the corresponding second physical block; and

(d) writing user data to the identified physical page.

22. A memory system according to claim 21 in which the memory controller is operative, upon receiving a write command specifying a write operation in respect of a plurality of logical pages of a given logical block, to determine said fullness criterion would be met if user data in respect of some, but not all, the specified logical pages is written to the first physical block, and if said determination is positive writing data in respect of some of said specified logical pages to the first physical block and data in respect of other of said logical pages to the second physical block.

23. (canceled)

24. (canceled)

25. (canceled)

26. (canceled)