Storage controller, data processing method and computer program product for reducing channel processor overhead by effcient cache slot management

• US 20080270689A1
• Filed: 06/26/2008
• Published: 10/30/2008
• Est. Priority Date: 09/14/2005
• Status: Active Grant

• Current Assignee: Youichi Gotoh
• Original Assignee: Youichi Gotoh
• Inventors: Gotoh, Youichi
• Granted Patent: US 7,886,114 B2
• Time in Patent Office: Days
• US Class Current: 711/113
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/262 configured as RAID
• CPC Class Codes: G06F 2212/263 Network storage, e.g. SAN or NAS
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache

Abstract

When a first channel processor from among a plurality of channel processors receives an I/O request from a host system, a second channel processor, which is to execute a part of the processing to respond to the I/O request, is selected from among the channel processors based on the LM directories of the respective channel processors. The selected second channel processor checks whether there is a cache hit. If there is a cache hit, it transfers the data from the cache memory to the buffer memory. The first channel processor then processes the I/O request using the data transferred to the buffer memory.

Claims

1. A storage controller comprising:

at least one channel control unit;

a cache memory connected to the at least one channel control unit via a cache switch and having cache slots;

at least one disk control unit connected to the cache memory via the cache switch and configured to perform control of a storage device,

wherein the at least one channel control unit includes;

a plurality of channel processors each configured to process a read/write request from a host system,

wherein the plurality of channel processors are connected with each other;

a local memory assigned to each of the plurality of channel processors for storing management information indicating whether data read and written by one of the channel processors exists in one of the cache slots of the cache memory,

wherein the management information stores hash values in corresponding relation to slot numbers each identifying one of the cache slots; and

a buffer memory, connected to the plurality of channel processors, for storing data transmitted between the plurality of channel processors,

wherein, when a first channel processor from among the plurality of channel processors receives a read request from the host system, the first channel processor selects a second channel processor from among the other channel processors, and the first channel processor transmits a distribution processing request to the second channel processor;

wherein upon receipt of the distribution processing request, the second channel processor checks whether a cache hit occurs based on the management information assigned to the second channel processor, and if the cache hit occurs, the second channel processor fetches the data from one of the cache slots of the cache memory and writes the fetched data in the buffer memory; and

wherein the first channel processor performs control of transmitting data written in the buffer memory to the host system.

2. The storage controller according to claim 1, wherein the first channel processor selects the second channel processor based on the management information stored in the local memory assigned to the first channel processor.

3. The storage controller according to claim 1, wherein the first channel processor selects the second channel processor based on a usage rate of each of the plurality of the channel processors.

4. The storage controller according to claim 1, wherein the first channel processor selects the second channel processor based on a slot number calculated based on an address designated by the read request, the slot number being associated with one of the cache slots.

5. The storage controller according to claim 1, wherein the first channel processor looks up the local memories assigned to the other channel processors, and the first channel processor selects the second channel processor from among the other processor that is associated with the local memory storing the management information indicating the data in accordance with the read request exists in the cache slots.

6. The storage controller according to claim 1, wherein the management information stored in each of the local memories includes director information managed by the plurality of channel processors.

7. The storage controller according to claim 1, wherein the first channel processor selects the second channel processor based on an access pattern of the host system.

8. The storage controller according to claim 1, wherein each of the plurality of channel processor writes load information in the corresponding local memory in accordance with a read/write request, and

wherein the first channel processor looks up the local memories assigned to the other channel processors, and the first channel processor selects the second channel processor from among the other channel processor based on the load information stored in the local memories.