SYSTEM AND METHOD FOR PROTECTING MEMORY DURING SYSTEM INITIALIZATION

• US 20080270776A1
• Filed: 04/27/2007
• Published: 10/30/2008
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Network Appliance Incorporated (NetApp, Inc.)
• Original Assignee: Network Appliance Incorporated (NetApp, Inc.)
• Inventors: Blood, Roger, Totolos, George
• Granted Patent: US 7,840,837 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A system and method for protecting memory during system initialization is provided. A complex programmable logic device (CPLD) is operatively interconnected with a multiplexer to enable control of a memory to be switched between a memory controller and the CPLD in response to error conditions. If an error condition is identified, the CPLD assumes control of the memory and activates a battery subsystem to provide memory refreshes until system re-initialization. Upon system bring-up, interactions between the BIOS and CPLD assure that protected memory is fully recovered by the system. The contents of memory will remain protected from any further faults that may occur during the bring-up sequence.

Claims

1. A method for protecting memory, the method comprising the steps of:

initializing a computer system;

determining whether the memory is currently storing preserved data;

in response to determining that the memory is not storing preserved data, setting a signal to cause a memory subsystem to persistently maintain contents of the memory during an error condition of the computer system; and

in response to determining that the memory is storing preserved data, persistently storing the stored data on a storage device.

2. The method of claim 1 wherein the storage device comprises a disk.

3. The method of claim 1 further comprising the steps of:

detecting a clean shutdown operation;

flushing data stored in the memory to the storage device; and

deactivating the signal, thereby causing the memory subsystem to cease preserving contents of the memory.

4. The method of claim 3 wherein the step of causing the memory subsystem to cease preserving contents of the memory further comprises the step of deactivating a battery subsystem.

5. The method of claim 1 wherein the memory subsystem comprises of the memory and a battery subsystem.

6. The method of claim 1 further comprising the steps of:

detecting a shutdown operation that is not a clean shutdown operation; and

placing the memory into a self refresh mode to preserve the contents of the memory.

7. The method of claim 6 further comprising the step of switching a multiplexer in a control path of the memory to thereby prevent a memory controller from accessing the memory.

8. The method of claim 6 further comprising the step of changing control of the memory to a customizable programmable logic device to issue commands that place the memory into a low-power mode.

9. The method of claim 1 wherein the computer system comprises a storage system.

10. The method of claim 1 wherein the memory comprises one or more dual inline memory modules (DIMMs).

11. A system for protecting memory, the system comprising:

means for initializing a computer system;

means for determining whether the memory is currently storing preserved data;

in response to determining that the memory is not storing preserved data, means for setting a signal to cause a memory subsystem to persistently maintain contents of the memory during an error condition of the computer system; and

in response to determining that the memory is storing preserved data, means for persistently storing the stored data on a storage device.

12. A system to preserve memory, the system comprising:

a memory switchable between a memory controller and a customizable program logic device (CPLD), the CPLD further coupled to a battery subsystem configured to enable refresh operations to the memory, the CPLD further configured to, in response to detecting an error condition, assuming control of the memory and placing the memory in a low-power, self-refresh state.

13. The system of claim 12 further comprising a basic input output system (BIOS) interconnected with the CPLD.

14. The system of claim 13 further comprising a valid signal between the BIOS and the CPLD, the valid signal identifying that the CPLD is protecting contents of the memory.

15. The system of claim 14 wherein, in response to detecting that the valid signal is set, the BIOS is configured to restore a set of registers associated with the memory.

16. The system of claim 15 wherein the BIOS is further configured to request that control of the memory be changed from the CPLD to the memory controller.

17. The system of claim 16 wherein the CPLD grants control of the memory to the memory controller by modifying a memory select signal to a multiplexer.

18. The system of claim 13 further comprising a disarm signal between the BIOS and the CPLD, the disarm signal configuring the CPLD to ignore error conditions.

19. The system of claim 12 further comprising an indicator configured to alert an administrator when the CPLD has assumed control of the memory.

20. The system of claim 12 wherein the CPLD assumes control of the memory by modifying a memory select signal to a multiplexer.

21. The system of claim 20 wherein the multiplexer comprise a field effect transistor.

22. The system of claim 12 wherein the error condition comprises a loss of main power.

23. The system of claim 12 wherein the error condition comprises an assertion of a system reset.

24. The system of claim 12 wherein the memory comprises one or more dual in line memory modules (DIMMs).

25. A method for protecting memory, the method comprising the steps of:

detecting a fault; and

in response to detection of the fault, performing, by a customizable program logic device (CPLD), an operation to protect contents of a memory.

26. The method of claim 25 wherein the operation comprises assuming control of the memory by the CPLD and placing the memory in a low-power, self-refresh state.

27. The method of claim 25 wherein the step of performing the operation ensures that invalid commands are not sent to the memory.

28. The method of claim 25 wherein the operation ensures that refresh commands are sent to the memory.