Method for Protecting Intellectual Property Cores on Field Programmable Gate Array

• US 20080270805A1
• Filed: 07/02/2008
• Published: 10/30/2008
• Est. Priority Date: 06/13/2001
• Status: Abandoned Application

• Current Assignee: Algotronix Ltd.
• Original Assignee: Algotronix Ltd.
• Inventors: Kean, Thomas A.
• Application Number:
  US12/166,716
• Publication Number:
  US 20080270805A1
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/125 by manipulating the program code, e.g. source code, compiled code, interpreted code, machine code
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06Q 30/06 Buying, selling or leasing transactions

Abstract

Techniques are used to protect intellectual property cores on field programmable gate arrays. An approach is to associate each field programmable gate array, or a limited number of field programmable gate arrays, with a secret key. Each field programmable gate array may only be properly configured or programmed by an appropriate encrypted bitstream (which includes one or more intellectual property cores). This encrypted bitstream has been encoded by or for the secret key associated with a particular FPGA. Other techniques are also presented in this application and include network-based, nonnetwork-based, software-based, layered, and other approaches. The techniques allow an intellectual property core vendor to charge a customer per-use or per-configuration of their intellectual property. This is because an encrypted bitstream is useable only in a limited number, possibly just one, of the integrated circuits.

Claims

1. A method comprising:

manufacturing field programmable gate array integrated circuits, each integrated circuit having an identification code and a secret cryptographic key; and

creating a database of identification codes and secret cryptographic keys, wherein a field programmable gate array integrated circuit with a particular identification code is configurable using a bitstream encrypted using a secret cryptographic key associated with the particular identification code;

wherein the encrypted bitstream configures the field programmable gate array integrated circuit with the particular identification code by programming a plurality of electrical switches in the field programmable gate array integrated circuit to create a circuit corresponding to a user design.