DIFFERENCE SIGNAL PATH TEST AND CHARACTERIZATION CIRCUIT

• US 20080270864A1
• Filed: 07/09/2008
• Published: 10/30/2008
• Est. Priority Date: 01/03/2005
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Yuen H., Joshi, Rajiv V.
• Application Number:
  US12/169,664
• Publication Number:
  US 20080270864A1
• Time in Patent Office: Days
• US Class Current: 714/735
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Claims

1. A test circuit for testing and characterizing circuit response to a difference signal, said test circuit comprising:

a data latch holding a data test value;

a voltage divider developing a difference signal representative of said test value;

one or more selectable circuits, at least one being a circuit under test selectively receiving said difference signal; and

a comparator comparing an output from each said circuit under test against an expected result.

2. A test circuit as in claim 1 individually testing each of a plurality of said selectable circuits, said test circuit further comprising:

a decoder selecting each of said plurality of selectable circuits as said circuit under test;

an enable circuit selectively enabling said circuit under test; and

a plurality of latches each of said plurality of latches latching results from a corresponding one of said plurality of selectable circuits.

3. A test circuit as in claim 2, wherein said comparator comprises:

a compare circuit comparing an output from said circuit under test against said expected result; and

an output latch latching results from said compare circuit.

4. A test circuit as in claim 3, wherein said decoder selects an input port in said comparator, an output of each of said plurality of latches being connected to a corresponding said input port.

5. A test circuit as in claim 4, said comparator further comprising an encoder, outputs of said plurality of latches being connected to input ports of said encoder, said encoder encoding one of said input ports selected by said decoder, said encoded one being compared in said compare circuit.

6. A test circuit as in claim 5, wherein said compare circuit comprises:

an inverting path; and

a non-inverting path, said expected result selectively traversing either of said inverting path and said non-inverting path, said encoder selecting between said inverting path and said non-inverting path.

7. A test circuit as in claim 6, wherein said inverting path and said non-inverting path share a common output, said common output providing said results from said comparator.

8. A test circuit as in claim 3, further comprising a local clock clocking said data latch, said sense enable circuit and said comparator.

9. A test circuit as in claim 1, wherein said voltage divider is a programmable voltage divider comprising:

a complementary data input receiving an input data signal;

a programmable resistor, a difference voltage developing across at least a portion of said programmable resistor, said difference voltage having an output signal polarity selected by said input data signal; and

a difference output select selectively providing said difference voltage as a difference signal output.

10. A test circuit as in claim 9, wherein said programmable resistor is an active resistance network.

11. A test circuit as in claim 10, wherein active resistors in said active resistance network are p-type field effect transistors (PFETs).

12. A test circuit as in claim 11, wherein said complementary data input gates two PFETs in said active resistance network, said difference voltage being the drain voltages of said two PFETs.

13. A test circuit as in claim 12, wherein a plurality of said PFETs in said active resistive network are selectively connected in parallel.

14. A test circuit as in claim 13, wherein remaining ones of said PFETs are selectively gated in series with selectively parallel said plurality of PFETs.

15. A test circuit as in claim 14, wherein pairs of said remaining ones of PFETs are selectively gated in parallel, parallel gated said remaining ones being gated in series with selectively parallel said plurality of PFETs.

16. A test circuit as in claim 9, wherein said programmable voltage divider further comprises selectable difference signal output ports, each of said one or more selectable circuits being connected to a corresponding difference signal output port.

17. A test circuit as in claim 9, wherein magnitude of said difference voltage across said portion of said programmable resistor is programmable.

18. A test circuit as in claim 9, wherein said complementary data input selects current flow direction through said portion of said programmable resistor.

19. A test circuit as in claim 9, wherein said difference voltage across said portion of said programmable resistor is a pair of signals providing said difference signal.

20. A test circuit as in claim 1, wherein said difference signal is provided as a pair of signals, a difference between said pair of signals being said difference signal.

21. A test circuit as in claim 1, wherein said one or more selectable circuits are sense amplifiers.

22. A sense amplifier test and characterizing circuit, said sensing circuit comprising:

an input data latch holding a data test value;

a voltage divider developing a difference signal representative of said test value;

a plurality of sense amplifiers selectively receiving said difference signal;

a decoder selecting a one of said plurality of sense amplifiers as receiving said difference signal;

a sense enable circuit selectively enabling said selected one;

a plurality of latches, each of said plurality of latches latching results from a corresponding one of said plurality of sense amplifiers; and

a comparator comparing latched said results from a latch corresponding to said selected one against said data test value.

23. A sense amplifier test and characterizing circuit as in claim 22, wherein said comparator comprises:

an encoder, outputs of said plurality of latches being connected to encoder input ports, said encoder encoding contents at one of said input ports selected by said decoder;

a compare circuit comparing the encoded said contents against said data test value; and

an output latch latching compare results from said compare circuit.

24. A sense amplifier test and characterizing circuit as in claim 23, wherein said compare circuit comprises:

an inverting path receiving said data test value; and

a non-inverting path receiving said data test value and in parallel with said inverting path, said data test value selectively traversing either of said inverting path and said non-inverting path, said encoded contents selecting between said inverting path and said non-inverting path.

25. A sense amplifier test and characterizing circuit as in claim 24, wherein a common output of said inverting path and said non-inverting path provides said compare results.

26. A sense amplifier test and characterizing circuit as in claim 25, further comprising a local clock clocking said input data latch, said sense enable circuit and said comparator.

27. A sense amplifier test and characterizing circuit as in claim 22, wherein said contents of said input data latch selects current flow direction through a portion of said voltage divider.

28. A sense amplifier test and characterizing circuit as in claim 22, wherein said voltage divider provides a pair of signals, a difference between said pair of signals being said difference signal.